57 lines
1.0 KiB
Verilog
57 lines
1.0 KiB
Verilog
module mul_const #(
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parameter CONSTS_WHOLE = 8,
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parameter CONSTS_FRAC = 40,
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parameter CONSTS_WID = CONSTS_WHOLE + CONSTS_FRAC,
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parameter IN_WHOLE = CONSTS_WHOLE,
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parameter IN_FRAC = CONSTS_FRAC,
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parameter IN_WID = IN_WHOLE + IN_FRAC
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) (
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input clk,
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input signed [IN_WID-1:0] inp,
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input signed [CONSTS_WID-1:0] const_in,
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input arm,
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output signed [CONSTS_WID-1:0] outp,
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output finished
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);
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localparam UNSAT_WID = CONSTS_WID + IN_WID;
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wire signed [UNSAT_WID-1:0] unsat;
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boothmul #(
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.A1_LEN(CONSTS_WID),
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.A2_LEN(IN_WID)
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) mul (
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.clk(clk),
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.arm(arm),
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.a1(const_in),
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.a2(inp),
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.outn(unsat),
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.fin(finished)
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);
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localparam RIGHTTRUNC_WID = UNSAT_WID - IN_FRAC;
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wire signed [RIGHTTRUNC_WID-1:0] rtrunc =
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unsat[UNSAT_WID-1:IN_FRAC];
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generate if (IN_WHOLE > 0) begin
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intsat #(
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.IN_LEN(RIGHTTRUNC_WID),
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.LTRUNC(IN_WHOLE)
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) sat (
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.inp(rtrunc),
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.outp(outp)
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);
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end else begin
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assign outp = rtrunc;
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end endgenerate
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`ifdef VERILATOR
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initial begin
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$dumpfile("mul_const.fst");
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$dumpvars();
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end
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`endif
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endmodule
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