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base
|
dac, adc switch and documentation
|
2023-04-04 15:10:32 -04:00 |
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control_loop
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add yosys synth test for control loop
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2023-03-20 13:57:42 -04:00 |
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raster
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arty.xdc for synth test
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2023-03-20 13:58:35 -04:00 |
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spi
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move preprocessed generation to common makefile
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2023-03-16 16:32:03 +00:00 |
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waveform
|
compile verilog
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2023-04-03 15:29:20 -04:00 |
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Makefile
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pass yosys
|
2023-03-15 17:08:55 -04:00 |
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testbench.hpp
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simulate waveform.v
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2023-03-15 06:24:28 +00:00 |
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util.hpp
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test and simulate spi_switch
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2023-03-14 15:42:41 +00:00 |
Peter McGoron
e19a626945