513 lines
20 KiB
Python
513 lines
20 KiB
Python
"""
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##########################################################################
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# Portions of this file incorporate code licensed under the
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# BSD 2-Clause License.
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#
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# Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2020 Antmicro <www.antmicro.com>
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# Copyright (c) 2022 Victor Suarez Rovere <suarezvictor@gmail.com>
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# BSD 2-Clause License
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#
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# Copyright (c) Copyright 2012-2022 Enjoy-Digital.
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# Copyright (c) Copyright 2012-2022 / LiteX-Hub community.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are met:
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#
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# 1. Redistributions of source code must retain the above copyright notice, this
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# list of conditions and the following disclaimer.
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#
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# 2. Redistributions in binary form must reproduce the above copyright notice,
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# this list of conditions and the following disclaimer in the documentation
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# and/or other materials provided with the distribution.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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##########################################################################
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# Copyright 2023-2024 (C) Peter McGoron
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#
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# This file is a part of Upsilon, a free and open source software project.
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# For license terms, refer to the files in `doc/copying` in the Upsilon
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# source distribution.
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"""
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# There is nothing fundamental about the Arty A7(35|100)T to this
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# design, but another eval board will require some porting.
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from migen import *
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import litex_boards.platforms.digilent_arty as board_spec
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from litex.soc.integration.builder import Builder
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from litex.build.generic_platform import IOStandard, Pins, Subsignal
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from litex.soc.integration.soc_core import SoCCore
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from litex.soc.integration.soc import SoCRegion, SoCBusHandler, SoCIORegion
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from litex.soc.cores.clock import S7PLL, S7IDELAYCTRL
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from litex.soc.interconnect.csr import AutoCSR, Module, CSRStorage, CSRStatus
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from litex.soc.interconnect.wishbone import Interface
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from litedram.phy import s7ddrphy
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from litedram.modules import MT41K128M16
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from litedram.frontend.dma import LiteDRAMDMAReader
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from liteeth.phy.mii import LiteEthPHYMII
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from math import log2, floor
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def minbits(n):
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""" Return the amount of bits necessary to store n. """
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return floor(log2(n) + 1)
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"""
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Keep this diagram up to date! This is the wiring diagram from the ADC to
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the named Verilog pins.
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Refer to `A7-constraints.xdc` for pin names.
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DAC: SS MOSI MISO SCK
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0: 1 2 3 4 (PMOD A top, right to left)
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1: 1 2 3 4 (PMOD A bottom, right to left)
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2: 1 2 3 4 (PMOD B top, right to left)
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3: 0 1 2 3 (Analog header)
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4: 0 1 2 3 (PMOD C top, right to left)
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5: 4 5 6 8 (Analog header)
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6: 1 2 3 4 (PMOD D top, right to left)
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7: 1 2 3 4 (PMOD D bottom, right to left)
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Outer chip header (C=CONV, K=SCK, D=SDO, XX=not connected)
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26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41
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C4 K4 D4 C5 K5 D5 XX XX C6 K6 D6 C7 K7 D7 XX XX
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C0 K0 D0 C1 K1 D1 XX XX C2 K2 D2 C3 K3 D3
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0 1 2 3 4 5 6 7 8 9 10 11 12 13
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The `io` list maps hardware pins to names used by the SoC
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generator. These pins are then connected to Verilog modules.
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If there is more than one pin in the Pins string, the resulting
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name will be a vector of pins.
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"""
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io = [
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("differntial_output_low", 0, Pins("J17 J18 K15 J15 U14 V14 T13 U13 B6 E5 A3"), IOStandard("LVCMOS33")),
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("dac_ss_L", 0, Pins("G13 D13 E15 F5 U12 D7 D4 E2"), IOStandard("LVCMOS33")),
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("dac_mosi", 0, Pins("B11 B18 E16 D8 V12 D5 D3 D2"), IOStandard("LVCMOS33")),
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("dac_miso", 0, Pins("A11 A18 D15 C7 V10 B7 F4 H2"), IOStandard("LVCMOS33")),
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("dac_sck", 0, Pins("D12 K16 C15 E7 V11 E6 F3 G2"), IOStandard("LVCMOS33")),
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("adc_conv", 0, Pins("V15 T11 N15 U18 U11 R10 R16 U17"), IOStandard("LVCMOS33")),
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("adc_sck", 0, Pins("U16 R12 M16 R17 V16 R11 N16 T18"), IOStandard("LVCMOS33")),
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("adc_sdo", 0, Pins("P14 T14 V17 P17 M13 R13 N14 R18"), IOStandard("LVCMOS33")),
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("module_reset", 0, Pins("D9"), IOStandard("LVCMOS33")),
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("test_clock", 0, Pins("P18"), IOStandard("LVCMOS33"))
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]
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class PreemptiveInterface(Module, AutoCSR):
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""" A preemptive interface is a manually controlled Wishbone interface
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that stands between multiple masters (potentially interconnects) and a
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single slave. A master controls which master (or interconnect) has access
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to the slave. This is to avoid bus contention by having multiple buses. """
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def __init__(self, masters_len, slave):
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"""
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:param masters_len: The amount of buses accessing this slave. This number
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must be greater than one.
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:param slave: The slave device. This object must have an Interface object
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accessable as ``bus``.
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"""
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assert masters_len > 1
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self.buses = []
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self.master_select = CSRStorage(masters_len, name='master_select', description='RW bitstring of which master interconnect to connect to')
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self.slave = slave
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for i in range(masters_len):
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# Add the slave interface each master interconnect sees.
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self.buses.append(Interface(data_width=32, address_width=32, addressing="byte"))
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self.comb += [
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self.buses[i].cti.eq(0),
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self.buses[i].bte.eq(0),
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]
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"""
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Construct a combinatorial case statement. In verilog, the if
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statment would look like
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always @ (*) case (master_select)
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1: begin
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// Bus assignments...
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end
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2: begin
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// Bus assignments...
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end
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// more cases:
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default:
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// assign everything to master 0
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end
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The If statement in Migen (Python HDL) is an object with a method
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called "ElseIf" and "Else", that return objects with the specified
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case attached. Instead of directly writing an If statement into
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the combinatorial block, the If statement is constructed in a
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for loop.
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The "assign_for_case" function constructs the body of the If
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statement. It assigns all output ports to avoid latches.
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"""
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def assign_for_case(i):
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asn = [ ]
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for j in range(masters_len):
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asn += [
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self.buses[i].cyc.eq(self.slave.bus.cyc if i == j else 0),
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self.buses[i].stb.eq(self.slave.bus.stb if i == j else 0),
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self.buses[i].we.eq(self.slave.bus.we if i == j else 0),
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self.buses[i].sel.eq(self.slave.bus.sel if i == j else 0),
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self.buses[i].adr.eq(self.slave.bus.adr if i == j else 0),
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self.buses[i].dat_w.eq(self.slave.bus.dat_w if i == j else 0),
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self.buses[i].ack.eq(self.slave.bus.ack if i == j else 0),
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self.buses[i].dat_r.eq(self.slave.bus.dat_r if i == j else 0),
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self.buses[i].cti.eq(0),
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self.buses[i].bte.eq(0),
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]
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return asn
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cases = {"default": assign_for_case(0)}
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for i in range(1, masters_len):
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cases[i] = assign_for_case(i)
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self.comb += Case(self.master_select.storage, cases)
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class SPIMaster(Module):
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def __init__(self, rst, miso, mosi, sck, ss,
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polarity = 0,
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phase = 0,
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ss_wait = 1,
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enable_miso = 1,
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enable_mosi = 1,
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spi_wid = 24,
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spi_cycle_half_wait = 1,
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):
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self.bus = Interface(data_width = 32, address_width=32, addressing="word")
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self.region = SoCIORegion(size=0x10, cached=False)
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self.comb += [
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self.bus.cti.eq(0),
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self.bus.bte.eq(0),
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]
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self.specials += Instance("spi_master_ss_wb",
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SS_WAIT = ss_wait,
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SS_WAIT_TIMER_LEN = minwid(ss_wait),
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CYCLE_HALF_WAIT = spi_cycle_half_wait,
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TIMER_LEN = minwid(spi_cycle_half_wait),
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WID = spi_wid,
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WID_LEN = minwid(spi_wid),
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ENABLE_MISO = enable_miso,
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ENABLE_MOSI = enable_mosi,
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POLARITY = polarity,
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PHASE = phase,
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i_clk = ClockSignal(),
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i_rst_L = rst,
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i_miso = miso,
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o_mosi = mosi,
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o_sck_wire = sck,
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o_ss_L = ss,
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i_wb_cyc = self.bus.cyc,
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i_wb_stb = self.bus.stb,
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i_wb_we = self.bus.we,
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i_wb_sel = self.bus.sel,
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i_wb_addr = self.bus.adr,
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i_wb_dat_w = self.bus.dat_w,
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o_wb_ack = self.bus.ack,
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o_wb_dat_r = self.bus.dat_r,
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)
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# TODO: Generalize CSR stuff
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class ControlLoopParameters(Module, AutoCSR):
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def __init__(self):
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self.cl_I = CSRStorage(32, description='Integral parameter')
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self.cl_P = CSRStorage(32, description='Proportional parameter')
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self.deltaT = CSRStorage(32, description='Wait parameter')
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self.setpt = CSRStorage(32, description='Setpoint')
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self.zset = CSRStatus(32, description='Set Z position')
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self.zpos = CSRStatus(32, description='Measured Z position')
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self.bus = Interface(data_width = 32, address_width = 32, addressing="word")
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self.region = SoCRegion(size=minbits(0x17), cached=False)
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self.comb += [
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self.bus.cti.eq(0),
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self.bus.bte.eq(0),
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]
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self.sync += [
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If(self.bus.cyc == 1 and self.bus.stb == 1 and self.bus.ack == 0,
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Case(self.bus.adr[0:4], {
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0x0: self.bus.dat_r.eq(self.cl_I.storage),
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0x4: self.bus.dat_r.eq(self.cl_P.storage),
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0x8: self.bus.dat_r.eq(self.deltaT.storage),
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0xC: self.bus.dat_r.eq(self.setpt.storage),
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0x10: If(self.bus.we,
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self.zset.status.eq(self.bus.dat_w)
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).Else(
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self.bus.dat_r.eq(self.zset.status)
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),
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0x14: If(self.bus.we,
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self.zpos.status.eq(self.bus.dat_w),
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).Else(
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self.bus.dat_r.eq(self.zpos.status)
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),
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}),
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self.bus.ack.eq(1),
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).Else(
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self.bus.ack.eq(0),
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)
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]
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class BRAM(Module):
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""" A BRAM (block ram) is a memory store that is completely separate from
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the system RAM. They are much smaller.
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"""
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def __init__(self, addr_mask, origin=None):
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"""
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:param addr_mask: Mask which defines the amount of bytes accessable
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by the BRAM.
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:param origin: Origin of the BRAM module region. This is seen by the
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subordinate master, not the usual master.
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"""
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self.bus = Interface(data_width=32, address_width=32, addressing="byte")
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# Non-IO (i.e. MMIO) regions need to be cached
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self.region = SoCRegion(origin=origin, size=addr_mask+1, cached=True)
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self.comb += [
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self.bus.cti.eq(0),
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self.bus.bte.eq(0),
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]
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self.specials += Instance("bram",
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p_ADDR_MASK = addr_mask,
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i_clk = ClockSignal(),
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i_wb_cyc = self.bus.cyc,
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i_wb_stb = self.bus.stb,
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i_wb_we = self.bus.we,
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i_wb_sel = self.bus.sel,
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i_wb_addr = self.bus.adr,
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i_wb_dat_w = self.bus.dat_w,
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o_wb_ack = self.bus.ack,
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o_wb_dat_r = self.bus.dat_r,
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)
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class PicoRV32(Module, AutoCSR):
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def __init__(self, bramwid=0x1000):
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self.submodules.params = params = ControlLoopParameters()
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self.submodules.bram = self.bram = bram = BRAM(bramwid-1, origin=0x10000)
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self.submodules.bram_iface = self.bram_iface = bram_iface = PreemptiveInterface(2, bram)
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# This is the PicoRV32 master
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self.masterbus = Interface(data_width=32, address_width=32, addressing="byte")
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self.resetpin = CSRStorage(1, name="picorv32_reset", description="PicoRV32 reset")
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self.trap = CSRStatus(1, name="picorv32_trap", description="Trap bit")
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self.ic = ic = SoCBusHandler(
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standard="wishbone",
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data_width=32,
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address_width=32,
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timeout=1e6,
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bursting=False,
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interconnect="shared",
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interconnect_register=True,
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reserved_regions={
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"picorv32_null_region": SoCRegion(origin=0,size=0x10000, mode="ro", cached=True),
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"picorv32_io": SoCIORegion(origin=0x100000, size=0x100, mode="rw", cached=False),
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},
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)
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ic.add_slave("picorv32_bram", bram_iface.buses[1], bram.region)
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ic.add_slave("picorv32_params", params.bus, params.region)
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ic.add_master("picorv32_master", self.masterbus)
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# NOTE: need to compile to these extact instructions
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self.specials += Instance("picorv32_wb",
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p_COMPRESSED_ISA = 1,
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p_ENABLE_MUL = 1,
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p_PROGADDR_RESET=0x10000,
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p_PROGADDR_IRQ=0x100010,
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p_REGS_INIT_ZERO = 1,
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o_trap = self.trap.status,
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i_wb_rst_i = ~self.resetpin.storage,
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i_wb_clk_i = ClockSignal(),
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o_wbm_adr_o = self.masterbus.adr,
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o_wbm_dat_o = self.masterbus.dat_r,
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i_wbm_dat_i = self.masterbus.dat_w,
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o_wbm_we_o = self.masterbus.we,
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o_wbm_sel_o = self.masterbus.sel,
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o_wbm_stb_o = self.masterbus.stb,
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i_wbm_ack_i = self.masterbus.ack,
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o_wbm_cyc_o = self.masterbus.cyc,
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o_pcpi_valid = Signal(),
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o_pcpi_insn = Signal(32),
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o_pcpi_rs1 = Signal(32),
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o_pcpi_rs2 = Signal(32),
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i_pcpi_wr = 0,
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i_pcpi_wait = 0,
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i_pcpi_rd = 0,
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i_pcpi_ready = 0,
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i_irq = 0,
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o_eoi = Signal(32),
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o_trace_valid = Signal(),
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o_trace_data = Signal(36),
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)
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def do_finalize(self):
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self.ic.finalize()
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jsondata = {}
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for region in self.ic.regions:
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d = self.ic.regions[region]
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jsondata[region] = {
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"origin": d.origin,
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"size": d.size,
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}
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with open('picorv32.json', 'w') as f:
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import json
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json.dump(jsondata, f)
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# Clock and Reset Generator
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# I don't know how this works, I only know that it does.
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq, with_dram, rst_pin):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_eth = ClockDomain()
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if with_dram:
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self.clock_domains.cd_sys4x = ClockDomain()
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self.clock_domains.cd_sys4x_dqs = ClockDomain()
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self.clock_domains.cd_idelay = ClockDomain()
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# Clk/Rst.
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clk100 = platform.request("clk100")
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rst = ~rst_pin if rst_pin is not None else 0
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# PLL.
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self.submodules.pll = pll = S7PLL(speedgrade=-1)
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self.comb += pll.reset.eq(rst | self.rst)
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pll.register_clkin(clk100, 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_eth, 25e6)
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self.comb += platform.request("eth_ref_clk").eq(self.cd_eth.clk)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
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if with_dram:
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_idelay, 200e6)
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# IdelayCtrl.
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if with_dram:
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
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class UpsilonSoC(SoCCore):
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def add_ip(self, ip_str, ip_name):
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for seg_num, ip_byte in enumerate(ip_str.split('.'),start=1):
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self.add_constant(f"{ip_name}{seg_num}", int(ip_byte))
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def add_picorv32(self):
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self.submodules.picorv32 = pr = PicoRV32()
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self.bus.add_slave("picorv32_master_bram", pr.bram_iface.buses[0],
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SoCRegion(size=pr.bram.region.size, cached=True))
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def __init__(self,
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variant="a7-100",
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local_ip="192.168.2.50",
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remote_ip="192.168.2.100",
|
|
tftp_port=6969):
|
|
sys_clk_freq = int(100e6)
|
|
platform = board_spec.Platform(variant=variant, toolchain="f4pga")
|
|
rst = platform.request("cpu_reset")
|
|
self.submodules.crg = _CRG(platform, sys_clk_freq, True, rst)
|
|
|
|
"""
|
|
These source files need to be sorted so that modules
|
|
that rely on another module come later. For instance,
|
|
`control_loop` depends on `control_loop_math`, so
|
|
control_loop_math.v comes before control_loop.v
|
|
|
|
If you want to add a new verilog file to the design, look at the
|
|
modules that it refers to and place it the files with those modules.
|
|
|
|
Since Yosys doesn't support modern Verilog, only put preprocessed
|
|
(if applicable) files here.
|
|
"""
|
|
platform.add_source("rtl/picorv32/picorv32.v")
|
|
platform.add_source("rtl/spi/spi_master.v")
|
|
platform.add_source("rtl/spi/spi_master_ss.v")
|
|
platform.add_source("rtl/spi/spi_master_ss_wb.v")
|
|
platform.add_source("rtl/bram/bram.v")
|
|
|
|
# SoCCore does not have sane defaults (no integrated rom)
|
|
SoCCore.__init__(self,
|
|
clk_freq=sys_clk_freq,
|
|
toolchain="symbiflow",
|
|
platform = platform,
|
|
bus_standard = "wishbone",
|
|
ident = f"Arty-{variant} F4PGA LiteX VexRiscV Zephyr - Upsilon",
|
|
bus_data_width = 32,
|
|
bus_address_width = 32,
|
|
bus_timeout = int(1e6),
|
|
cpu_type = "vexriscv_smp",
|
|
cpu_count = 1,
|
|
cpu_variant="linux",
|
|
integrated_rom_size=0x20000,
|
|
integrated_sram_size = 0x2000,
|
|
csr_data_width=32,
|
|
csr_address_width=14,
|
|
csr_paging=0x800,
|
|
csr_ordering="big",
|
|
timer_uptime = True)
|
|
# This initializes the connection to the physical DRAM interface.
|
|
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
|
|
memtype = "DDR3",
|
|
nphases = 4,
|
|
sys_clk_freq = sys_clk_freq)
|
|
# Synchronous dynamic ram. This is what controls all access to RAM.
|
|
# This houses the "crossbar", which negotiates all RAM accesses to different
|
|
# modules, including the verilog interfaces (waveforms etc.)
|
|
self.add_sdram("sdram",
|
|
phy = self.ddrphy,
|
|
module = MT41K128M16(sys_clk_freq, "1:4"),
|
|
l2_cache_size = 8192
|
|
)
|
|
|
|
# Initialize Ethernet
|
|
self.submodules.ethphy = LiteEthPHYMII(
|
|
clock_pads = platform.request("eth_clocks"),
|
|
pads = platform.request("eth"))
|
|
self.add_ethernet(phy=self.ethphy, dynamic_ip=True)
|
|
|
|
# Initialize network information
|
|
self.add_ip(local_ip, "LOCALIP")
|
|
self.add_ip(remote_ip, "REMOTEIP")
|
|
self.add_constant("TFTP_SERVER_PORT", tftp_port)
|
|
|
|
# Add pins
|
|
platform.add_extension(io)
|
|
self.add_picorv32()
|
|
|
|
def main():
|
|
""" Add modifications to SoC variables here """
|
|
soc =UpsilonSoC(variant="a7-35")
|
|
builder = Builder(soc, csr_json="csr.json", compile_software=True)
|
|
builder.build()
|
|
|
|
if __name__ == "__main__":
|
|
main()
|