45 lines
1.2 KiB
Verilog
45 lines
1.2 KiB
Verilog
/* This module is used to simulate direct memory access, where only
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* a small amount of memory is valid to read.
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*/
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module dma_sim #(
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parameter RAM_WID = 32,
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parameter RAM_WORD_WID = 16,
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parameter RAM_REAL_START = 32'h12340,
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parameter RAM_CNTR_LEN = 12,
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parameter TOTAL_RAM_WORD_MINUS_ONE = 4095,
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parameter DELAY_CNTR_LEN = 8,
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parameter DELAY_TOTAL = 12
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) (
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input clk,
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/* DMA interface */
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input [RAM_WID-1:0] ram_dma_addr,
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output reg [RAM_WORD_WID-1:0] ram_word,
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input ram_read,
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output reg ram_valid,
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/*- Verilator interface */
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input [RAM_WORD_WID-1:0] backing_store[TOTAL_RAM_WORD_MINUS_ONE:0]
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);
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reg [DELAY_CNTR_LEN-1:0] delay_cntr = 0;
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always @ (posedge clk) begin
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if (!ram_read) begin
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delay_cntr <= 0;
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ram_valid <= 0;
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end else if (delay_cntr < DELAY_TOTAL) begin
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delay_cntr <= delay_cntr + 1;
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end else if (!ram_valid) begin
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if (ram_dma_addr < RAM_REAL_START || ram_dma_addr > RAM_REAL_START + 2*TOTAL_RAM_WORD_MINUS_ONE) begin
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$display("ram_dma_addr %x out of bounds", ram_dma_addr);
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$stop();
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end else begin
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ram_word <= backing_store[(RAM_CNTR_LEN)'((ram_dma_addr - RAM_REAL_START)/2)];
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ram_valid <= 1;
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end
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end
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end
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endmodule
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