143 lines
2.6 KiB
Verilog
143 lines
2.6 KiB
Verilog
/* Copyright 2023 (C) Peter McGoron
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* This file is a part of Upsilon, a free and open source software project.
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* For license terms, refer to the files in `doc/copying` in the Upsilon
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* source distribution.
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*/
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`include "control_loop_cmds.vh"
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module control_loop_sim_top #(
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parameter ADC_WID = 18,
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parameter ADC_WID_SIZ = 5,
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parameter ADC_POLARITY = 1,
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parameter ADC_PHASE = 0,
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parameter DAC_POLARITY = 0,
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parameter DAC_PHASE = 1,
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parameter DAC_DATA_WID = 20,
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parameter DAC_WID = 24,
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parameter DAC_WID_SIZ = 5,
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parameter CONSTS_WHOLE = 21,
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parameter CONSTS_FRAC = 43,
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`define CONSTS_WID (CONSTS_WHOLE + CONSTS_FRAC)
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parameter CONSTS_SIZ = 7,
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parameter DELAY_WID = 16
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)(
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input clk,
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input rst_L,
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output in_loop,
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output [DAC_DATA_WID-1:0] curset,
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output dac_err,
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input [ADC_WID-1:0] measured_value,
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output request,
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input fulfilled,
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output adc_err,
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input [`CONSTS_WID-1:0] word_into_loop,
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output [`CONSTS_WID-1:0] word_outof_loop,
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input start_cmd,
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output finish_cmd,
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input [`CONTROL_LOOP_CMD_WIDTH-1:0] cmd
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);
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/* Emulate a control loop environment with simulator controlled
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SPI interfaces.
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*/
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wire adc_miso;
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wire adc_sck;
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wire adc_ss_L;
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/* ADC */
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adc_sim #(
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.WID(ADC_WID),
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.WID_LEN(5),
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.POLARITY(ADC_POLARITY),
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.PHASE(ADC_PHASE)
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) adc (
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.clk(clk),
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.rst_L(rst_L),
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.indat(measured_value),
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.request(request),
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.fulfilled(fulfilled),
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.err(adc_err),
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.miso(adc_miso),
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.sck(adc_sck),
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.ss_L(adc_ss_L)
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);
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wire dac_miso;
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wire dac_mosi;
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wire dac_ss_L;
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wire dac_sck;
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/* DAC */
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dac_sim #(
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.WID(DAC_WID),
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.DATA_WID(DAC_DATA_WID),
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.WID_LEN(5),
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.POLARITY(DAC_POLARITY),
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.PHASE(DAC_PHASE)
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) dac (
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.clk(clk),
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.rst_L(rst_L),
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.curset(curset),
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.mosi(dac_mosi),
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.miso(dac_miso),
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.sck(dac_sck),
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.ss_L(dac_ss_L),
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.err(dac_err)
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);
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control_loop #(
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.ADC_WID(ADC_WID),
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.ADC_WID_SIZ(ADC_WID_SIZ),
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.ADC_POLARITY(ADC_POLARITY),
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.ADC_PHASE(ADC_PHASE),
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/* Keeping cycle half wait and conv wait the same
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* since it doesn't matter for this simulation */
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.CONSTS_WHOLE(CONSTS_WHOLE),
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.CONSTS_FRAC(CONSTS_FRAC),
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.CONSTS_SIZ(CONSTS_SIZ),
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.DELAY_WID(DELAY_WID),
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.DAC_WID(DAC_WID),
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.DAC_WID_SIZ(DAC_WID_SIZ),
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.DAC_DATA_WID(DAC_DATA_WID),
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.DAC_POLARITY(DAC_POLARITY),
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.DAC_PHASE(DAC_PHASE)
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) cloop (
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.clk(clk),
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.rst_L(rst_L),
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.in_loop(in_loop),
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.dac_mosi(dac_mosi),
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.dac_miso(dac_miso),
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.dac_ss_L(dac_ss_L),
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.dac_sck(dac_sck),
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.adc_miso(adc_miso),
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.adc_conv_L(adc_ss_L),
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.adc_sck(adc_sck),
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.word_in(word_into_loop),
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.word_out(word_outof_loop),
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.start_cmd(start_cmd),
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.finish_cmd(finish_cmd),
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.cmd(cmd)
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);
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`ifdef VERILATOR
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initial begin
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$dumpfile("control_loop.fst");
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$dumpvars;
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end
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`endif
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endmodule
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`undefineall
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