133 lines
2.9 KiB
Verilog
133 lines
2.9 KiB
Verilog
/* Copyright 2023 (C) Peter McGoron
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* This file is a part of Upsilon, a free and open source software project.
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* For license terms, refer to the files in `doc/copying` in the Upsilon
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* source distribution.
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*/
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module waveform_sim #(
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parameter DAC_WID = 24,
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parameter DAC_WID_SIZ = 5,
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parameter DAC_POLARITY = 0,
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parameter DAC_PHASE = 1,
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parameter DAC_CYCLE_HALF_WAIT = 10,
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parameter DAC_CYCLE_HALF_WAIT_SIZ = 4,
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parameter DAC_SS_WAIT = 5,
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parameter DAC_SS_WAIT_SIZ = 3,
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parameter TIMER_WID = 32,
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parameter WORD_WID = 20,
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parameter WORD_AMNT_WID = 11,
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parameter [WORD_AMNT_WID-1:0] WORD_AMNT = 2047,
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parameter RAM_REAL_START = 32'h12340,
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parameter RAM_CNTR_LEN = 12,
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parameter TOTAL_RAM_WORD_MINUS_ONE = 4095,
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parameter DELAY_CNTR_LEN = 8,
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parameter DELAY_TOTAL = 12,
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parameter RAM_WID = 32,
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parameter RAM_WORD_WID = 16,
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parameter RAM_WORD_INCR = 2
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) (
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input clk,
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input rst_L,
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input arm,
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input halt_on_finish,
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output waveform_finished,
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output running,
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input [TIMER_WID-1:0] time_to_wait,
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/* User interface */
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input refresh_start,
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input [RAM_WID-1:0] start_addr,
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output reg refresh_finished,
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output [DAC_WID-1:0] from_master,
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output finished,
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input rdy,
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output spi_err,
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input[RAM_WORD_WID-1:0] backing_store [TOTAL_RAM_WORD_MINUS_ONE:0]
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);
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wire sck;
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wire ss_L;
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wire mosi;
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spi_slave_no_write #(
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.WID(DAC_WID),
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.WID_LEN(DAC_WID_SIZ),
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.POLARITY(DAC_POLARITY),
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.PHASE(DAC_PHASE)
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) slave (
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.clk(clk),
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.sck(sck),
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.rst_L(rst_L),
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.ss_L(ss_L),
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.mosi(mosi),
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.from_master(from_master),
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.finished(finished),
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.rdy(rdy),
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.err(spi_err)
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);
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wire [RAM_WID-1:0] ram_dma_addr;
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wire [RAM_WORD_WID-1:0] ram_word;
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wire ram_read;
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wire ram_valid;
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dma_sim #(
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.RAM_WID(RAM_WID),
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.RAM_WORD_WID(RAM_WORD_WID),
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.RAM_REAL_START(RAM_REAL_START),
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.RAM_CNTR_LEN(RAM_CNTR_LEN),
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.TOTAL_RAM_WORD_MINUS_ONE(TOTAL_RAM_WORD_MINUS_ONE),
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.DELAY_CNTR_LEN(DELAY_CNTR_LEN),
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.DELAY_TOTAL(DELAY_TOTAL)
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) dma_sim (
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.clk(clk),
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.ram_dma_addr(ram_dma_addr),
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.ram_word(ram_word),
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.ram_read(ram_read),
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.ram_valid(ram_valid),
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.backing_store(backing_store)
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);
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waveform #(
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.DAC_WID(DAC_WID),
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.DAC_WID_SIZ(DAC_WID_SIZ),
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.DAC_POLARITY(DAC_POLARITY),
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.DAC_PHASE(DAC_PHASE),
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.DAC_CYCLE_HALF_WAIT(DAC_CYCLE_HALF_WAIT),
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.DAC_CYCLE_HALF_WAIT_SIZ(DAC_CYCLE_HALF_WAIT_SIZ),
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.DAC_SS_WAIT(DAC_SS_WAIT),
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.DAC_SS_WAIT_SIZ(DAC_SS_WAIT_SIZ),
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.TIMER_WID(TIMER_WID),
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.WORD_WID(WORD_WID),
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.WORD_AMNT_WID(WORD_AMNT_WID),
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.WORD_AMNT(WORD_AMNT),
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.RAM_WID(RAM_WID),
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.RAM_WORD_WID(RAM_WORD_WID),
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.RAM_WORD_INCR(RAM_WORD_INCR)
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) waveform (
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.clk(clk),
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.arm(arm),
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.rst_L(rst_L),
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.halt_on_finish(halt_on_finish),
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.running(running),
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.finished(waveform_finished),
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.time_to_wait(time_to_wait),
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.refresh_start(refresh_start),
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.start_addr(start_addr),
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.refresh_finished(refresh_finished),
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.ram_dma_addr(ram_dma_addr),
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.ram_word(ram_word),
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.ram_read(ram_read),
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.ram_valid(ram_valid),
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.mosi(mosi),
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.sck(sck),
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.ss_L(ss_L)
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);
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endmodule
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`undefineall
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