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Free and open source SoC for Scanning Probe Microscopy
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NickAA f3e8415171 Added Menu to control_loop_sim.cpp 
I was able to add the menu to the file and I fixed some bugs that came up.
For some reason the seed value (a.k.a. P value) does not accept strings or char values so I left the set_value
as is and same for the I value I don't know what the value is that is within the set_value. But everything seems
to work the way it's intended to.
 		2023-01-29 16:25:24 -05:00
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firmware Added Menu to control_loop_sim.cpp 2023-01-29 16:25:24 -05:00
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README.md

upsilon

Upsilon is a 100% free and open source STM/AFM controller for FPGAs.

Organization

The project is split into hardware (firmware), kernel (software), and client software (client).

Hardware uses Verilog, LiteX and F4PGA to implement the Soft CPU (Risc-V), hardware communication, PI control loop, image scanning, and tip autoapproach.

Kernel implements the network communication between the hardware and the client software.

The client software receives and interprets data from the hardware.

License

GNU GPL v3.0 or later. Other portions are dual licensed under the CERN OHL-v2-S, or permissive licenses: please view all COPYING files for more legal information.

See also