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| author |  Peter McGoron
| 2023-04-21 17:39:18 +0000 |
|---|---|---|
| committer | Peter McGoron
| 2023-04-21 17:39:18 +0000 |
| commit | 619734f54eaa8ab12214174b97e3bfca5be9ca1a (patch) | |
| tree | 5e081f59ff6b0ffe9abaa95dd40aea8048e86a4c /README.md | |
| parent | license and bump version (diff) | |
Diffstat (limited to '')
| -rw-r--r-- | README.md | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -5,7 +5,7 @@ Verilog using the [Booth Algorithm][1]. [1]: https://en.wikipedia.org/wiki/Booth%27s_multiplication_algorithm -This design has been sucessfully synthesized with F4PGA +This design (v1.0) has been sucessfully synthesized with F4PGA (`5aafae65883e95e41de2d0294729662dbe0a34f5`) on a Digilent Arty A7-35T running at a clock speed of 100MHz. The test design is in `arty_test`. |