diff options
| author | 2023-02-07 17:46:44 +0000 | |
|---|---|---|
| committer | 2023-02-07 17:46:44 +0000 | |
| commit | f6e8c62f9e00210930bf222c077abef6c6d7cb34 (patch) | |
| tree | bc6b04e06d6338b3fed63ec4f1ad2d704ee6dd19 /asm/test.py | |
| parent | add label test (diff) | |
move python
Diffstat (limited to 'asm/test.py')
| -rw-r--r-- | asm/test.py | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/asm/test.py b/asm/test.py new file mode 100644 index 0000000..e86b508 --- /dev/null +++ b/asm/test.py @@ -0,0 +1,42 @@ +from creole import * +import unittest + +class ProgramTest(unittest.TestCase): + def test_oneline(self): + p = Program() + p.parse_asm_line("PUSH r0") + b = p() + self.assertEqual(b, b'\x01\xC2\x80\x00') + def test_large_reg(self): + p = Program(regnum=0x8000000) + p.parse_asm_line("PUSH r134217727") + b = p() + self.assertEqual(b, b'\x01\xFC\x87\xbf\xbf\xbf\xbf\x00') + def test_two(self): + p = Program() + p.parse_asm_line("PUSH r1") + p.parse_asm_line("ADD r1 5 6") + b = p() + self.assertEqual(b, b'\x01\xC2\x81\x00\x03\xC2\x81\xC0\x85\xC0\x86\x00') + def test_label(self): + p = Program() + b_ex = bytes() + p.parse_asm_line("CLB l0") + b_ex = b_ex + b'\x07\xC0\x80\x00' + p.parse_asm_line("pop r0") + b_ex = b_ex + b'\x02\xC2\x80\x00' + p.parse_asm_line("pop r1") + b_ex = b_ex + b'\x02\xC2\x81\x00' + p.parse_asm_line("mul r2 r0 r1") + b_ex = b_ex + b'\x04\xC2\x82\xC2\x80\xC2\x81\x00' + p.parse_asm_line("push r2") + b_ex = b_ex + b'\x01\xC2\x82\x00' + p.parse_asm_line("push r2") + b_ex = b_ex + b'\x01\xC2\x82\x00' + p.parse_asm_line("jl l0 r2 10") + b_ex = b_ex + b'\x06\xC0\x80\xC2\x82\xC0\x8A\x00' + b = p() + self.assertEqual(b, b_ex) + +if __name__ == "__main__": + unittest.main() |
