diff options
| author | 2023-02-18 16:05:09 +0000 | |
|---|---|---|
| committer | 2023-02-18 16:05:09 +0000 | |
| commit | 48827c5b747eca6d56555f69cae37291feb5fcda (patch) | |
| tree | 063bc21af510fe961a7002678e0cdf9dbb8bc228 /asm/test.py | |
| parent | add data, remove labels and make jumps absolute (diff) | |
adjust python assembler to new API
Diffstat (limited to 'asm/test.py')
| -rw-r--r-- | asm/test.py | 27 |
1 files changed, 10 insertions, 17 deletions
diff --git a/asm/test.py b/asm/test.py index ed78398..f2c2277 100644 --- a/asm/test.py +++ b/asm/test.py @@ -19,20 +19,13 @@ class PushTest(unittest.TestCase): def test_parse_push_reg(self): p = Program() p.parse_asm_line("push r5") - b = p() - self.assertEqual(b, b'\x01\xC2\x85\x00') - ins = ffi.parse_line(b) - self.assertEqual(ins[0], Instruction.PUSH.opcode) - self.assertEqual(ins[1][0], (1,5)) + self.assertEqual(p(), b'\x01\xC2\x85\x00') def test_parse_push_imm(self): p = Program() p.parse_asm_line("push 5") b = p() self.assertEqual(b, b'\x01\xC0\x85\x00') - ins = ffi.parse_line(b) - self.assertEqual(ins[0], Instruction.PUSH.opcode) - self.assertEqual(ins[1][0], (0,5)) def test_parse_push_catch_typecheck_push_lab(self): p = Program() @@ -175,7 +168,7 @@ class AddTest(unittest.TestCase): def test_exec_add(self): p = Program() p.parse_asm_line("add r0 1 1") - ex = ffi.Environment(p()) + ex = ffi.Environment(p) self.assertEqual(ex(), ffi.RunRet.STOP) self.assertEqual(ex.cenv.reg[0], 2) @@ -201,18 +194,18 @@ class AddTest(unittest.TestCase): def test_exec_add_throw_lab_1(self): p = Program() with self.assertRaises(TypecheckException) as cm: - p.parse_asm_line("add r0 l6 7") + p.parse_asm_line("add r0 .label 7") self.assertEqual(cm.exception.argtype, ArgType.VAL) - self.assertEqual(cm.exception.sarg, 'l6') + self.assertEqual(cm.exception.sarg, '.label') self.assertEqual(cm.exception.i, 1) self.assertEqual(cm.exception.opcode, 3) def test_exec_add_throw_lab_2(self): p = Program() with self.assertRaises(TypecheckException) as cm: - p.parse_asm_line("add r0 12 l24") + p.parse_asm_line("add r0 12 .ab") self.assertEqual(cm.exception.argtype, ArgType.VAL) - self.assertEqual(cm.exception.sarg, 'l24') + self.assertEqual(cm.exception.sarg, '.ab') self.assertEqual(cm.exception.i, 2) self.assertEqual(cm.exception.opcode, 3) @@ -307,18 +300,18 @@ class DivTest(unittest.TestCase): def test_exec_div_throw_lab_1(self): p = Program() with self.assertRaises(TypecheckException) as cm: - p.parse_asm_line("div r0 l123 456") + p.parse_asm_line("div r0 .qqweq 456") self.assertEqual(cm.exception.argtype, ArgType.VAL) - self.assertEqual(cm.exception.sarg, 'l123') + self.assertEqual(cm.exception.sarg, '.qqweq') self.assertEqual(cm.exception.i, 1) self.assertEqual(cm.exception.opcode, 5) def test_exec_div_throw_lab_2(self): p = Program() with self.assertRaises(TypecheckException) as cm: - p.parse_asm_line("div r5 1919 l24") + p.parse_asm_line("div r5 1919 .24") self.assertEqual(cm.exception.argtype, ArgType.VAL) - self.assertEqual(cm.exception.sarg, 'l24') + self.assertEqual(cm.exception.sarg, '.24') self.assertEqual(cm.exception.i, 2) self.assertEqual(cm.exception.opcode, 5) |
