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authorGravatar Peter McGoron 2023-02-12 20:21:25 +0000
committerGravatar Peter McGoron 2023-02-12 20:21:25 +0000
commit4f14e48ba5d3ff1329b92f847d27c2a1c75f0a1e (patch)
tree6a244314ac54df2c3555f08623b44a3620533600 /asm
parentadd immediate signed and unsigned tests (diff)
more loop tests
Diffstat (limited to '')
-rw-r--r--asm/creole.py2
-rw-r--r--asm/test.py54
2 files changed, 55 insertions, 1 deletions
diff --git a/asm/creole.py b/asm/creole.py
index d68958e..bbcbf8a 100644
--- a/asm/creole.py
+++ b/asm/creole.py
@@ -125,7 +125,7 @@ class TypecheckLenException(Exception):
self.argtypelen = argtypelen
def __str__(self):
return f'''\
-arguments {insargs} to opcode {self.opcode} not of length {self.argtypelen}\
+arguments {self.insargs} to opcode {self.opcode} not of length {self.argtypelen}\
'''
class TypecheckException(Exception):
""" Exception thrown when an argument to an instruction are of the
diff --git a/asm/test.py b/asm/test.py
index f68ff1c..19778b5 100644
--- a/asm/test.py
+++ b/asm/test.py
@@ -338,6 +338,58 @@ class LabelTest(unittest.TestCase):
self.assertEqual(ex.getreg(0), 0)
self.assertEqual(ex.getreg(1), 30)
+ def test_signed_jmp(self):
+ p = Program()
+ p.parse_lines([
+ "mov r0 30",
+ "mov r1 0",
+ "CLB l0",
+ "add r0 r0 -1",
+ "add r1 r1 1",
+ "jls l0 -30 r0"
+ ])
+ ex = ffi.Environment(p())
+ self.assertEqual(ex(), ffi.RunRet.STOP)
+ self.assertEqual(ex.getreg(0, signed=True), -30)
+ self.assertEqual(ex.getreg(1), 60)
+
+ def test_jeq(self):
+ p = Program()
+ p.parse_lines([
+ "mov r0 50",
+ "mov r1 0",
+ "CLB l0",
+ "add r1 r1 1",
+ "mul r2 r0 -1",
+ "add r2 r2 r1",
+ "jne l0 r2 0"
+ ])
+ ex = ffi.Environment(p())
+ self.assertEqual(ex(), ffi.RunRet.STOP)
+ self.assertEqual(ex.getreg(0, signed=True), 50)
+ self.assertEqual(ex.getreg(1), 50)
+ self.assertEqual(ex.getreg(2), 0)
+
+ def test_nested_loop(self):
+ p = Program()
+ p.parse_lines([
+ "mov r0 0", # outer loop counter
+ "mov r2 0", # total iteration counter
+ "CLB l0",
+ "mov r1 0", # inner loop counter
+ "CLB l1",
+ "add r1 r1 1",
+ "add r2 r2 1",
+ "jl l1 r1 50",
+ "add r0 r0 1",
+ "jl l0 r0 50"
+ ])
+ ex = ffi.Environment(p())
+ self.assertEqual(ex(), ffi.RunRet.STOP)
+ self.assertEqual(ex.getreg(0), 50)
+ self.assertEqual(ex.getreg(1), 50)
+ self.assertEqual(ex.getreg(2), 50*50)
+
class ProgramTest(unittest.TestCase):
def test_exec_simple_reg(self):
p = Program()
@@ -359,6 +411,7 @@ class ProgramTest(unittest.TestCase):
self.assertEqual(ex(), ffi.RunRet.STOP)
self.assertEqual(ex.getreg(0, signed=sgn), i)
+ @unittest.skip("slow")
def test_parse_imm_compile(self):
self.range_test(0, 0x1000)
self.range_test(0x1000, 0x1100)
@@ -370,6 +423,7 @@ class ProgramTest(unittest.TestCase):
self.range_test(0x8000000, 0x8000100)
self.range_test(0xFFFFFF00, 0x100000000)
+ @unittest.skip("slow")
def test_parse_imm_signed(self):
self.range_test(0, 0x1000, sgn=True)
self.range_test(0x1000, 0x1100, sgn=True)