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Hardware / VexRiscv
Assembly 0 0
A FPGA friendly 32 bit RISC-V CPU implementation
fpga verilog soc softcore spinalhdl cpu vhdl riscv
Updated 2024-09-06 05:00:10 -04:00
Hardware / litex
C 0 0
Build your hardware, easily!
fpga hardware system-on-chip
Updated 2024-09-06 02:32:11 -04:00
Hardware / litex-boards
Python 0 0
LiteX boards files
Updated 2024-09-04 16:06:40 -04:00
Hardware / liteeth
Python 0 0
Small footprint and configurable Ethernet core
Updated 2024-09-04 08:48:34 -04:00
Hardware / litedram
Python 0 0
Small footprint and configurable DRAM core
Updated 2024-09-02 08:39:41 -04:00
peter / define-namespace
Scheme 0 0
R5RS portable library for a subset of R7RS define-library
Updated 2024-07-29 21:21:10 -04:00
Hardware / litescope
Python 0 0
Small footprint and configurable embedded FPGA logic analyzer
Updated 2024-07-25 04:48:27 -04:00
peter / http2https
Python 0 0
HTTP to HTTPS proxy
Updated 2024-07-19 06:56:03 -04:00
Hardware / f4pga
Python 0 0
FOSS Flow For FPGA
documentation sphinx symbiflow
Updated 2024-07-17 20:17:53 -04:00
peter / universalservice
C 0 0
Garbage collectors in C
Updated 2024-07-16 19:55:39 -04:00
peter / Flatrate Archived
C 0 0
C89 lisp implementation
Updated 2024-06-23 01:07:03 -04:00
Hardware / picorv32
Verilog 0 0
PicoRV32 - A Size-Optimized RISC-V CPU
Updated 2024-06-17 02:20:13 -04:00
Lab_NHMFL / upsilon-docker Archived
Makefile 0 0
Upsilon build scripts using docker
Updated 2024-06-02 23:08:32 -04:00
Lab_NHMFL / upsilon
Verilog 0 0
Free and open source SoC for Scanning Probe Microscopy
Updated 2024-06-02 22:48:20 -04:00
clib / aatree.h
C 0 0
single file, intrusive AA-tree balanced tree structure in C
Updated 2024-06-02 22:27:23 -04:00
peter / reference-man-pages
Roff 0 0
Mandoc man pages for scientific reference
Updated 2024-06-02 21:50:30 -04:00
Hardware / f4pga-examples
Verilog 0 0
Example designs showing different ways to use F4PGA toolchains.
fpga f4pga fpga-designs litex symbiflow-toolchains verilog conda-packages vexriscv
Updated 2024-03-27 07:22:52 -04:00
peter / verilog_random
C++ 0 0
Random number generators in verilog
Updated 2024-02-20 20:33:34 -05:00
peter / spi
Verilog 0 0
Verilog SPI
Updated 2024-01-27 23:09:00 -05:00
peter / wlb Archived
C 0 0
Windows Local Backup
Updated 2023-12-12 18:21:02 -05:00