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peter/ SAHP
Scheme 0 0
Singly Ad-hoc Polymorphic Procedures with Scope
Updated 2025-03-06 18:36:17 -05:00
peter/ GR-notebook
0 0
Notebook to calculate Christoffel symbols tensors for general relativity
Updated 2025-02-27 15:48:33 -05:00
peter/ weight-balanced-trees
Scheme 0 0
R7RS weight balanced trees
Updated 2025-02-17 15:00:50 -05:00
peter/ sexpr-srfi-64-runner
Scheme 0 0
Test runner for SRFI-64 that generates tunable verbose output in SEXPR form
Updated 2025-02-16 19:43:35 -05:00
peter/ srfi-252-egg
0 0
Property testing
Updated 2025-02-14 17:43:18 -05:00
peter/ srfi-194-egg
0 0
SRFI 194 Egg for CHICKEN
Updated 2025-02-13 20:27:18 -05:00
peter/ market
Scheme 0 0
A dialect of Markdown that is easier to parse
Updated 2025-02-04 10:29:50 -05:00
peter/ cond-values
Scheme 0 0
depreceated! use cond-thunk instead
Updated 2025-01-29 18:09:36 -05:00
Hardware/ litex
C 0 0
Build your hardware, easily!
fpga hardware system-on-chip
Updated 2025-01-03 15:57:29 -05:00
Hardware/ liteeth
Python 0 0
Small footprint and configurable Ethernet core
Updated 2025-01-02 12:25:14 -05:00
peter/ gamma-scheme
Scheme 0 0
Gamma Scheme is R7RS with delimited continuations.
Updated 2024-12-31 19:00:32 -05:00
peter/ cond-thunk
Scheme 0 0
Macros for abstracting conditional branches and an extension to cond-values
Updated 2024-12-31 17:37:20 -05:00
Hardware/ litex-boards
Python 0 0
LiteX boards files
Updated 2024-12-30 14:15:59 -05:00
peter/ container-iterators
Scheme 0 0
R7RS functional iterators over containers
Updated 2024-12-28 23:23:36 -05:00
peter/ sris
Scheme 0 0
RIS parser and handler in Scheme
Updated 2024-12-28 11:20:35 -05:00
Hardware/ f4pga
Python 0 0
FOSS Flow For FPGA
documentation sphinx symbiflow
Updated 2024-12-09 19:22:45 -05:00
peter/ brainfuck2scheme
Scheme 0 0
Compile Brainfuck to R5RS
Updated 2024-11-19 12:47:56 -05:00
Hardware/ VexRiscv
Assembly 0 0
A FPGA friendly 32 bit RISC-V CPU implementation
fpga verilog soc softcore spinalhdl cpu vhdl riscv
Updated 2024-11-15 05:47:51 -05:00
peter/ UNSLISP
Scheme 0 0
R7RS Scheme LISP compiler for GLLV bytecode, written to work in R3RS
Updated 2024-10-13 22:11:36 -04:00
Hardware/ litedram
Python 0 0
Small footprint and configurable DRAM core
Updated 2024-09-27 03:34:36 -04:00