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Hardware / VexRiscv
Assembly 0 0
A FPGA friendly 32 bit RISC-V CPU implementation
fpga verilog soc softcore spinalhdl cpu vhdl riscv
Updated 2024-11-15 05:47:51 -05:00
Lab_NHMFL / upsilon
Verilog 0 0
Free and open source SoC for Scanning Probe Microscopy
Updated 2024-06-02 22:48:20 -04:00