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Hardware / VexRiscv

Assembly 0 0

A FPGA friendly 32 bit RISC-V CPU implementation

fpga verilog soc softcore spinalhdl cpu vhdl riscv

Updated 2024-09-06 05:00:10 -04:00

Hardware / f4pga-examples

Verilog 0 0

Example designs showing different ways to use F4PGA toolchains.

fpga f4pga fpga-designs litex symbiflow-toolchains verilog conda-packages vexriscv

Updated 2024-03-27 07:22:52 -04:00

peter / verilog_random

C++ 0 0

Random number generators in verilog

Updated 2024-02-20 20:33:34 -05:00

peter / spi

Verilog 0 0

Verilog SPI

Updated 2024-01-27 23:09:00 -05:00

peter / boothmul

Python 0 0

Verilog Booth Multiplier

Updated 2023-04-21 13:41:11 -04:00