boothmul/arty_test/README.md

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2022-10-29 22:24:51 -04:00
This test requires LiteX 2022.08. You will need to define `DEBUG` in the `boothmul.v`
file for the logic analyzer to work correctly.
Run `python3 soc.py` to build the design. Afterwards, load the design. Then run
litex_server --uart --uart-port /dev/ttyUSB1
afterwards run
python3 hardtest.py
This will generate two .vcd files, which you can check to verify that the multiplier
is working.