From 619734f54eaa8ab12214174b97e3bfca5be9ca1a Mon Sep 17 00:00:00 2001
From: Peter McGoron <code@mcgoron.com>
Date: Fri, 21 Apr 2023 17:39:18 +0000
Subject: [PATCH] add reset pin

---
 README.md  |  2 +-
 boothmul.v | 10 ++++++++--
 sim.cpp    | 34 ++++++++++++++++++++++++----------
 3 files changed, 33 insertions(+), 13 deletions(-)

diff --git a/README.md b/README.md
index 322233b..d947e91 100644
--- a/README.md
+++ b/README.md
@@ -5,7 +5,7 @@ Verilog using the [Booth Algorithm][1].
 
 [1]: https://en.wikipedia.org/wiki/Booth%27s_multiplication_algorithm
 
-This design has been sucessfully synthesized with F4PGA
+This design (v1.0) has been sucessfully synthesized with F4PGA
 (`5aafae65883e95e41de2d0294729662dbe0a34f5`) on a Digilent Arty A7-35T
 running at a clock speed of 100MHz. The test design is in `arty_test`.
 
diff --git a/boothmul.v b/boothmul.v
index b6b96d5..5583004 100644
--- a/boothmul.v
+++ b/boothmul.v
@@ -1,4 +1,4 @@
-/* Booth Multiplication v1.0
+/* Booth Multiplication v1.1
  * Written by Peter McGoron, 2022.
  *
  * This source describes Open Hardware and is licensed under the
@@ -25,6 +25,7 @@ module boothmul
 )
 (
 	input clk,
+	input rst_L,
 	input arm,
 	input [A1_LEN-1:0] a1,
 	input [A2_LEN-1:0] a2,
@@ -104,7 +105,12 @@ assign debug_state = loop_accul;
 `endif
 
 always @ (posedge clk) begin
-	if (!arm) begin
+	if (!rst_L) begin
+		loop_accul <= 0;
+		fin <= 0;
+		p <= 0;
+		a1_reg <= 0;
+	end else if (!arm) begin
 		loop_accul <= 0;
 		fin <= 0;
 	end else if (loop_accul == 0) begin
diff --git a/sim.cpp b/sim.cpp
index 7edf0bf..6195f09 100644
--- a/sim.cpp
+++ b/sim.cpp
@@ -29,14 +29,27 @@ static void run_clock() {
 	main_time++;
 }
 
-static void run(word i, word j) {
+static void run(word i, word j, bool reset_in_middle) {
 	// Processor is twos-compliment
 	mod->a1 = i;
 	mod->a2 = j;
 	mod->arm = 1;
 
-	while (!mod->fin)
-		run_clock();
+	if (!reset_in_middle) {
+		while (!mod->fin)
+			run_clock();
+	} else {
+		int i = 0;
+		while (!mod->fin) {
+			if (i == 10) {
+				mod->rst_L = 0;
+			} else if (i == 20) {
+				mod->rst_L = 1;
+			}
+			run_clock();
+			i++;
+		}
+	}
 
 	dword expected = (dword) i * (dword) j;
 	if (mod->outn != expected) {
@@ -55,16 +68,17 @@ int main(int argc, char **argv) {
 
 	mod->clk = 0;
 	mod->arm = 0;
+	mod->rst_L = 1;
 	run_clock();
 
-	run(minint, minint);
-	run(minint, maxint);
-	run(maxint, minint);
-	run(maxint, maxint);
+	run(minint, minint, false);
+	run(minint, maxint, false);
+	run(maxint, minint, false);
+	run(maxint, maxint, false);
 
-	for (word i = -20; i < 20; i++) {
-		for (word j = - 20; j < 20; j++) {
-			run(i, j);
+	for (word i = -40; i < 40; i++) {
+		for (word j = - 40; j < 40; j++) {
+			run(i, j, rand() % 1);
 		}
 	}