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boothmul
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This commit is contained in:
Peter McGoron 2023-04-21 17:39:18 +00:00
parent a70737a671
commit 619734f54e
3 changed files with 33 additions and 13 deletions
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2
README.md
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@ -5,7 +5,7 @@ Verilog using the [Booth Algorithm][1].
[1]: https://en.wikipedia.org/wiki/Booth%27s_multiplication_algorithm [1]: https://en.wikipedia.org/wiki/Booth%27s_multiplication_algorithm
This design has been sucessfully synthesized with F4PGA This design (v1.0) has been sucessfully synthesized with F4PGA
(`5aafae65883e95e41de2d0294729662dbe0a34f5`) on a Digilent Arty A7-35T (`5aafae65883e95e41de2d0294729662dbe0a34f5`) on a Digilent Arty A7-35T
running at a clock speed of 100MHz. The test design is in `arty_test`. running at a clock speed of 100MHz. The test design is in `arty_test`.

10
boothmul.v
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@ -1,4 +1,4 @@
/* Booth Multiplication v1.0 /* Booth Multiplication v1.1
* Written by Peter McGoron, 2022. * Written by Peter McGoron, 2022.
* *
* This source describes Open Hardware and is licensed under the * This source describes Open Hardware and is licensed under the
@ -25,6 +25,7 @@ module boothmul
) )
( (
input clk, input clk,
input rst_L,
input arm, input arm,
input [A1_LEN-1:0] a1, input [A1_LEN-1:0] a1,
input [A2_LEN-1:0] a2, input [A2_LEN-1:0] a2,
@ -104,7 +105,12 @@ assign debug_state = loop_accul;
`endif `endif
always @ (posedge clk) begin always @ (posedge clk) begin
if (!arm) begin if (!rst_L) begin
loop_accul <= 0;
fin <= 0;
p <= 0;
a1_reg <= 0;
end else if (!arm) begin
loop_accul <= 0; loop_accul <= 0;
fin <= 0; fin <= 0;
end else if (loop_accul == 0) begin end else if (loop_accul == 0) begin

34
sim.cpp
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@ -29,14 +29,27 @@ static void run_clock() {
main_time++; main_time++;
} }
static void run(word i, word j) { static void run(word i, word j, bool reset_in_middle) {
// Processor is twos-compliment // Processor is twos-compliment
mod->a1 = i; mod->a1 = i;
mod->a2 = j; mod->a2 = j;
mod->arm = 1; mod->arm = 1;
while (!mod->fin) if (!reset_in_middle) {
run_clock(); while (!mod->fin)
run_clock();
} else {
int i = 0;
while (!mod->fin) {
if (i == 10) {
mod->rst_L = 0;
} else if (i == 20) {
mod->rst_L = 1;
}
run_clock();
i++;
}
}
dword expected = (dword) i * (dword) j; dword expected = (dword) i * (dword) j;
if (mod->outn != expected) { if (mod->outn != expected) {
@ -55,16 +68,17 @@ int main(int argc, char **argv) {
mod->clk = 0; mod->clk = 0;
mod->arm = 0; mod->arm = 0;
mod->rst_L = 1;
run_clock(); run_clock();
run(minint, minint); run(minint, minint, false);
run(minint, maxint); run(minint, maxint, false);
run(maxint, minint); run(maxint, minint, false);
run(maxint, maxint); run(maxint, maxint, false);
for (word i = -20; i < 20; i++) { for (word i = -40; i < 40; i++) {
for (word j = - 20; j < 20; j++) { for (word j = - 40; j < 40; j++) {
run(i, j); run(i, j, rand() % 1);
} }
} }