add reset pin
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a70737a671
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@ -5,7 +5,7 @@ Verilog using the [Booth Algorithm][1].
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[1]: https://en.wikipedia.org/wiki/Booth%27s_multiplication_algorithm
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This design has been sucessfully synthesized with F4PGA
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This design (v1.0) has been sucessfully synthesized with F4PGA
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(`5aafae65883e95e41de2d0294729662dbe0a34f5`) on a Digilent Arty A7-35T
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running at a clock speed of 100MHz. The test design is in `arty_test`.
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10
boothmul.v
10
boothmul.v
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@ -1,4 +1,4 @@
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/* Booth Multiplication v1.0
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/* Booth Multiplication v1.1
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* Written by Peter McGoron, 2022.
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*
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* This source describes Open Hardware and is licensed under the
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@ -25,6 +25,7 @@ module boothmul
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)
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(
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input clk,
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input rst_L,
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input arm,
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input [A1_LEN-1:0] a1,
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input [A2_LEN-1:0] a2,
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@ -104,7 +105,12 @@ assign debug_state = loop_accul;
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`endif
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always @ (posedge clk) begin
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if (!arm) begin
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if (!rst_L) begin
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loop_accul <= 0;
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fin <= 0;
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p <= 0;
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a1_reg <= 0;
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end else if (!arm) begin
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loop_accul <= 0;
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fin <= 0;
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end else if (loop_accul == 0) begin
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34
sim.cpp
34
sim.cpp
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@ -29,14 +29,27 @@ static void run_clock() {
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main_time++;
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}
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static void run(word i, word j) {
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static void run(word i, word j, bool reset_in_middle) {
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// Processor is twos-compliment
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mod->a1 = i;
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mod->a2 = j;
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mod->arm = 1;
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while (!mod->fin)
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run_clock();
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if (!reset_in_middle) {
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while (!mod->fin)
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run_clock();
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} else {
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int i = 0;
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while (!mod->fin) {
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if (i == 10) {
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mod->rst_L = 0;
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} else if (i == 20) {
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mod->rst_L = 1;
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}
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run_clock();
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i++;
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}
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}
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dword expected = (dword) i * (dword) j;
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if (mod->outn != expected) {
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@ -55,16 +68,17 @@ int main(int argc, char **argv) {
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mod->clk = 0;
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mod->arm = 0;
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mod->rst_L = 1;
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run_clock();
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run(minint, minint);
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run(minint, maxint);
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run(maxint, minint);
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run(maxint, maxint);
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run(minint, minint, false);
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run(minint, maxint, false);
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run(maxint, minint, false);
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run(maxint, maxint, false);
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for (word i = -20; i < 20; i++) {
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for (word j = - 20; j < 20; j++) {
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run(i, j);
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for (word i = -40; i < 40; i++) {
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for (word j = - 40; j < 40; j++) {
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run(i, j, rand() % 1);
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}
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}
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