Booth multiplier
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commit
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VERILATOR_FLAGS = --cc --exe -x-assign fast -Wall -DBOOTH_SIM \
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-GA1_LEN=16 -GA2_LEN=16 -GA2LEN_SIZ=5
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VERILATOR_INPUT = boothmul.v sim.cpp
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obj_dir/Vboothmul: obj_dir/Vboothmul.mk obj_dir/Vboothmul.cpp \
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obj_dir/Vboothmul.h sim.cpp
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cd obj_dir && make -f Vboothmul.mk
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obj_dir/Vboothmul.mk: $(VERILATOR_INPUT)
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verilator $(VERILATOR_FLAGS) $(VERILATOR_INPUT)
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/* Booth Multiplication
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* Written by Peter McGoron, 2022.
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*/
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module boothmul
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#(
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parameter A1_LEN = 32,
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parameter A2_LEN = 32,
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// AZLEN_SIZ = floor(log2(A2_LEN + 2) + 1).
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// It must be able to store A2_LEN + 2.
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parameter A2LEN_SIZ = 6
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)
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(
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input clk,
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input arm,
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input [A1_LEN-1:0] a1,
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input [A2_LEN-1:0] a2,
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output [A1_LEN+A2_LEN-1:0] outn,
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output reg fin
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);
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/***********************
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* Booth Parameters
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**********************/
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localparam OUT_LEN = A1_LEN + A2_LEN;
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localparam REG_LEN = OUT_LEN + 2;
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/* The Booth multiplication algorithm is a sequential algorithm for
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* twos-compliment integers.
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*
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* Let REG_LEN be equal to 1 + len(a1) + len(a2) + 1.
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* Let P, S, and A be of length REG_LEN.
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* Let A = a1 << len(a2) + 1, where a1 sign extends to the upper bit.
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* Let S = -a1 << len(a2) + 1, where a1 sign extens to the upper bit.
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* Let P = a2 << 1.
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*
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* Repeat the following len(a2) times:
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* case(P[1:0])
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* 2'b00, 2'b11: P <= P >>> 1;
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* 2'b01: P <= (P + A) >>> 1;
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* 2'b10: P <= (P + S) >>> 1;
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* endcase
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* The final value is P[REG_LEN-2:1].
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*
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* Wires and registers of REG_LEN length are organized like:
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*
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* /Overflow bit
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* [M][ REG_LEN ][0]
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* [M][ A1_LEN ][ A2_LEN ][0]
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*/
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reg signed [REG_LEN-1:0] a;
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reg signed [REG_LEN-1:0] s;
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reg signed [REG_LEN-1:0] p = 0;
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assign outn[OUT_LEN-1:0] = p[REG_LEN-2:1];
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/**********************
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* Loop Implementation
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*********************/
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reg[A2LEN_SIZ-1:0] loop_accul = 0;
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always @ (posedge clk) begin
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if (!arm) begin
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loop_accul <= 0;
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fin <= 0;
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end else if (loop_accul == 0) begin
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p[0] <= 0;
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p[A2_LEN:1] <= a2;
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p[REG_LEN-1:A2_LEN+1] <= 0;
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a[A2_LEN:0] <= 0;
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a[REG_LEN-2:A2_LEN + 1] <= a1;
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a[REG_LEN-1] <= a1[A1_LEN-1]; // Sign extension
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s[A2_LEN:0] <= 0;
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// Extend before negation to ensure size
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s[REG_LEN-1:A2_LEN+1] <= ~{a1[A1_LEN-1],a1} + 1;
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loop_accul <= loop_accul + 1;
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end else if (loop_accul < A2_LEN + 1) begin
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/* The loop counter starts from 1, so it must go to
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* A2_LEN + 1 exclusive.
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* (i = 0; i < len; i++)
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* becomes (i = 1; i < len + 1; i++)
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*/
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loop_accul <= loop_accul + 1;
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case (p[1:0])
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2'b00, 2'b11: p <= p >>> 1;
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2'b10: p <= (p + s) >>> 1;
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2'b01: p <= (p + a) >>> 1;
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endcase
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end else begin
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fin <= 1;
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end
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end
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`ifdef BOOTH_SIM
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initial begin
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$dumpfile("booth.vcd");
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$dumpvars;
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end
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`endif
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endmodule
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@ -0,0 +1,76 @@
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#include <memory>
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#include <limits>
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#include <cstdint>
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#include <iostream>
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#include <verilated.h>
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#include "Vboothmul.h"
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using word = int16_t;
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using dword = int32_t;
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constexpr word minint = std::numeric_limits<word>::min();
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constexpr word maxint = std::numeric_limits<word>::max();
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uint32_t main_time = 0;
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double sc_time_stamp() {
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return main_time;
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}
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Vboothmul *mod;
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static void run_clock() {
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mod->clk = !mod->clk;
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mod->eval();
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main_time++;
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mod->clk = !mod->clk;
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mod->eval();
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main_time++;
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}
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static void run(word i, word j) {
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// Processor is twos-compliment
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mod->a1 = i;
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mod->a2 = j;
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mod->arm = 1;
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while (!mod->fin)
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run_clock();
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dword expected = (dword) i * (dword) j;
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if (mod->outn != expected) {
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std::cout << i << "*" << j << "=" << expected
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<< "(" << mod->outn << ")" << std::endl;
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}
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mod->arm = 0;
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run_clock();
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}
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int main(int argc, char **argv) {
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Verilated::commandArgs(argc, argv);
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// Verilated::traceEverOn(true);
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mod = new Vboothmul;
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mod->clk = 0;
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mod->arm = 0;
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run_clock();
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run(minint, minint);
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run(minint, maxint);
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run(maxint, minint);
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run(maxint, maxint);
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for (word i = -20; i < 20; i++) {
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for (word j = - 20; j < 20; j++) {
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run(i, j);
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}
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}
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mod->final();
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delete mod;
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return 0;
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}
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