# Booth Multiplier

Sequentially multiply two signed twos-compliment integers in
Verilog using the [Booth Algorithm][1].

[1]: https://en.wikipedia.org/wiki/Booth%27s_multiplication_algorithm

This design (v1.0) has been sucessfully synthesized with F4PGA
(`5aafae65883e95e41de2d0294729662dbe0a34f5`) on a Digilent Arty A7-35T
running at a clock speed of 100MHz. The test design is in `arty_test`.

## License

All source code is licensed under the CERN-OHL-W v2 or later, unless
otherwise noted.

## Usage

Set parameters `A1_LEN` and `A2_LEN` to the argument size of the
first and second integer. Set `A2LEN_SIZ` equal to
`floor(log2(A2_LEN) + 1)`.

After inputting each integer, pulse `arm` and wait until `fin` goes
high to retreive the output in `outn`.

## Simulating

Simulation is done with Verilator. Run `make`.