# This file is licensed under the BSD 2 Clause License.
# (c) Peter McGoron 2022
# Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
# Copyright (c) 2020 Antmicro <www.antmicro.com>
# Copyright (c) 2022 Victor Suarez Rovere <suarezvictor@gmail.com>
# BSD 2-Clause License
# 
# Copyright (c) Copyright 2012-2022 Enjoy-Digital.
# Copyright (c) Copyright 2012-2022 / LiteX-Hub community.
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# modification, are permitted provided that the following conditions are met:
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# 1. Redistributions of source code must retain the above copyright notice, this
#    list of conditions and the following disclaimer.
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#    this list of conditions and the following disclaimer in the documentation
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from migen import *
from litex.soc.integration.builder import Builder
from litex.soc.integration.soc_core import SoCCore
from litex.soc.cores.clock import S7PLL, S7IDELAYCTRL
from litex.soc.interconnect.csr import AutoCSR, Module, CSRStorage, CSRStatus
from litex_boards.platforms.digilent_arty import Platform
import math

from litedram.phy import s7ddrphy
from litedram.modules import MT41K128M16
from liteeth.phy.mii import LiteEthPHYMII

# Clock and Reset Generator
class _CRG(Module):
    def __init__(self, platform, sys_clk_freq, with_dram=True, with_rst=True):
        self.rst = Signal()
        self.clock_domains.cd_sys       = ClockDomain()
        self.clock_domains.cd_eth       = ClockDomain()
        if with_dram:
            self.clock_domains.cd_sys4x     = ClockDomain()
            self.clock_domains.cd_sys4x_dqs = ClockDomain()
            self.clock_domains.cd_idelay    = ClockDomain()

        # Clk/Rst.
        clk100 = platform.request("clk100")
        rst    = ~platform.request("cpu_reset") if with_rst else 0

        # PLL.
        self.submodules.pll = pll = S7PLL(speedgrade=-1)
        self.comb += pll.reset.eq(rst | self.rst)
        pll.register_clkin(clk100, 100e6)
        pll.create_clkout(self.cd_sys, sys_clk_freq)
        pll.create_clkout(self.cd_eth, 25e6)
        self.comb += platform.request("eth_ref_clk").eq(self.cd_eth.clk)
        platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
        if with_dram:
            pll.create_clkout(self.cd_sys4x,     4*sys_clk_freq)
            pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
            pll.create_clkout(self.cd_idelay,    200e6)

        # IdelayCtrl.
        if with_dram:
            self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)

class Multiplier(Module, AutoCSR):
	def __init__(self, constwid = 48, inwid = 48):
		a2lensiz = math.ceil(math.log2(inwid) + 1) + 1
		self.const_in = CSRStorage(constwid, description="Multiplier Constant")
		self.inval = CSRStorage(inwid, description="Multiplier 2nd Input")
		self.outval = CSRStatus(constwid + inwid, description="Multiplier Output")
		self.p = CSRStatus(constwid + inwid + 2, description="P")
		self.a = CSRStatus(constwid + inwid + 2, description="A")
		self.s = CSRStatus(constwid + inwid + 2, description="S")
		self.state = CSRStatus(a2lensiz, description="State")
		self.arm = CSRStorage(1, description="Arm")
		self.fin = CSRStatus(1, description="Multiplier Finished")

		self.specials += Instance("boothmul",
			p_A1_LEN = constwid,
			p_A2_LEN = inwid,
			p_A2LEN_SIZ = math.ceil(math.log2(inwid) + 1) + 1,
			i_clk = ClockSignal("sys"),
			i_a1 = self.const_in.storage,
			i_a2 = self.inval.storage,
			o_outn = self.outval.status,
			i_arm = self.arm.storage,
			o_fin = self.fin.status,
			o_debug_a = self.a.status,
			o_debug_s = self.s.status,
			o_debug_p = self.p.status,
			o_debug_state = self.state.status
		)

class TestPlatform(SoCCore, AutoCSR):
	def __init__(self, platform, constwid = 8, inwid = 8):
		sys_clk_freq = int(100e6)
		SoCCore.__init__(self,
			clk_freq=sys_clk_freq,
			cpu_type = None,
			integrated_sram_size = 0x2000,
			with_uart = False,
			platform = platform
		)
		from litescope import LiteScopeAnalyzer
		self.submodules.crg = _CRG(platform, sys_clk_freq, True)
		self.submodules.multiplier = Multiplier(constwid, inwid)
		self.add_uartbone(name="serial", baudrate=115200)
		self.submodules.analyzer = LiteScopeAnalyzer(
			[
				self.multiplier.p.status,
				self.multiplier.a.status,
				self.multiplier.s.status,
				self.multiplier.inval.storage,
				self.multiplier.const_in.storage,
				self.multiplier.outval.status,
				self.multiplier.arm.storage,
				self.multiplier.fin.status,
				self.multiplier.state.status,
			], depth=64, clock_domain = "sys", samplerate = sys_clk_freq,
			csr_csv = "analyzer.csv"
		)

platform = Platform(variant="a7-35", toolchain="symbiflow")
platform.add_source("../boothmul.v")
builder = Builder(TestPlatform(platform), csr_csv="csr.csv")
builder.build()