# Construct SoC.

from migen import ClockSignal
from litex_boards.targets.digilent_arty import BaseSoC
from litex_boards.platforms.digilent_arty import Platform, Builder
from litescope import LiteScopeAnalyzer

platform = Platform(variant="a7-100")
platform.add_source("../boothmul.v")

class TestPlatform(BaseSoC):
	def __init__(self, platform, constwid = 48, inwid = 48):
		BaseSoC.__init__(
			with_uartbone = True,
			toolchain = "symbiflow",
			platform = platform
		)

	self.const_in = CSRStorage(constwid)
	self.inval = CSRStorage(inwid)
	self.outval = CSRStatus(const_wid + inwid)
	self.arm = CSRStorage(arm)
	self.fin = CSRStatus(arm)

	self.specials += Instance("boothmul",
		p_A1_LEN = constwid,
		p_A2_LEN = inwid,
		A2LEN_SIZ = math.ceil(math.log2(inwid) + 1) + 1,
		clk = ClockSignal(),
		a1 = self.const_in.storage,
		a2 = self.inval.storage,
		outn = self.outval.status,
		i_arm = self.arm.storage,
		fin = self.fin.status
	)

builder = Builder(TestPlatform(platform), csr_csv="csr.csv")
builder.build()