139 lines
5.7 KiB
Python
139 lines
5.7 KiB
Python
# This file is licensed under the BSD 2 Clause License.
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# (c) Peter McGoron 2022
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# Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2020 Antmicro <www.antmicro.com>
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# Copyright (c) 2022 Victor Suarez Rovere <suarezvictor@gmail.com>
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# BSD 2-Clause License
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#
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# Copyright (c) Copyright 2012-2022 Enjoy-Digital.
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# Copyright (c) Copyright 2012-2022 / LiteX-Hub community.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are met:
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#
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# 1. Redistributions of source code must retain the above copyright notice, this
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# list of conditions and the following disclaimer.
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#
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# 2. Redistributions in binary form must reproduce the above copyright notice,
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# this list of conditions and the following disclaimer in the documentation
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# and/or other materials provided with the distribution.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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from migen import *
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from litex.soc.integration.builder import Builder
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from litex.soc.integration.soc_core import SoCCore
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from litex.soc.cores.clock import S7PLL, S7IDELAYCTRL
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from litex.soc.interconnect.csr import AutoCSR, Module, CSRStorage, CSRStatus
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from litex_boards.platforms.digilent_arty import Platform
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import math
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from litedram.phy import s7ddrphy
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from litedram.modules import MT41K128M16
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from liteeth.phy.mii import LiteEthPHYMII
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# Clock and Reset Generator
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq, with_dram=True, with_rst=True):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_eth = ClockDomain()
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if with_dram:
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self.clock_domains.cd_sys4x = ClockDomain()
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self.clock_domains.cd_sys4x_dqs = ClockDomain()
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self.clock_domains.cd_idelay = ClockDomain()
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# Clk/Rst.
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clk100 = platform.request("clk100")
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rst = ~platform.request("cpu_reset") if with_rst else 0
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# PLL.
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self.submodules.pll = pll = S7PLL(speedgrade=-1)
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self.comb += pll.reset.eq(rst | self.rst)
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pll.register_clkin(clk100, 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_eth, 25e6)
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self.comb += platform.request("eth_ref_clk").eq(self.cd_eth.clk)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
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if with_dram:
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_idelay, 200e6)
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# IdelayCtrl.
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if with_dram:
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
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class Multiplier(Module, AutoCSR):
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def __init__(self, constwid = 48, inwid = 48):
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a2lensiz = math.ceil(math.log2(inwid) + 1) + 1
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self.const_in = CSRStorage(constwid, description="Multiplier Constant")
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self.inval = CSRStorage(inwid, description="Multiplier 2nd Input")
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self.outval = CSRStatus(constwid + inwid, description="Multiplier Output")
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self.p = CSRStatus(constwid + inwid + 2, description="P")
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self.a = CSRStatus(constwid + inwid + 2, description="A")
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self.s = CSRStatus(constwid + inwid + 2, description="S")
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self.state = CSRStatus(a2lensiz, description="State")
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self.arm = CSRStorage(1, description="Arm")
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self.fin = CSRStatus(1, description="Multiplier Finished")
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self.specials += Instance("boothmul",
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p_A1_LEN = constwid,
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p_A2_LEN = inwid,
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p_A2LEN_SIZ = math.ceil(math.log2(inwid) + 1) + 1,
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i_clk = ClockSignal("sys"),
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i_a1 = self.const_in.storage,
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i_a2 = self.inval.storage,
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o_outn = self.outval.status,
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i_arm = self.arm.storage,
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o_fin = self.fin.status,
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o_debug_a = self.a.status,
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o_debug_s = self.s.status,
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o_debug_p = self.p.status,
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o_debug_state = self.state.status
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)
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class TestPlatform(SoCCore, AutoCSR):
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def __init__(self, platform, constwid = 8, inwid = 8):
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sys_clk_freq = int(100e6)
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SoCCore.__init__(self,
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clk_freq=sys_clk_freq,
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cpu_type = None,
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integrated_sram_size = 0x2000,
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with_uart = False,
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platform = platform
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)
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from litescope import LiteScopeAnalyzer
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self.submodules.crg = _CRG(platform, sys_clk_freq, True)
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self.submodules.multiplier = Multiplier(constwid, inwid)
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self.add_uartbone(name="serial", baudrate=115200)
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self.submodules.analyzer = LiteScopeAnalyzer(
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[
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self.multiplier.p.status,
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self.multiplier.a.status,
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self.multiplier.s.status,
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self.multiplier.inval.storage,
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self.multiplier.const_in.storage,
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self.multiplier.outval.status,
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self.multiplier.arm.storage,
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self.multiplier.fin.status,
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self.multiplier.state.status,
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], depth=64, clock_domain = "sys", samplerate = sys_clk_freq,
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csr_csv = "analyzer.csv"
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)
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platform = Platform(variant="a7-35", toolchain="symbiflow")
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platform.add_source("../boothmul.v")
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builder = Builder(TestPlatform(platform), csr_csv="csr.csv")
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builder.build()
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