From 00e9d12c716da6ff05142522a49798f22aab90cd Mon Sep 17 00:00:00 2001
From: Peter McGoron <code@mcgoron.com>
Date: Sun, 12 Feb 2023 19:28:48 +0000
Subject: [PATCH] add mov and unconditional jump

---
 asm/creole.py | 37 ++++++++++++++++++++++++-------------
 asm/test.py   | 22 ++++++++++++++++++++++
 2 files changed, 46 insertions(+), 13 deletions(-)

diff --git a/asm/creole.py b/asm/creole.py
index 9fdd242..d68958e 100644
--- a/asm/creole.py
+++ b/asm/creole.py
@@ -147,21 +147,23 @@ class Instruction(Enum):
 	    arguments. The first argument is the opcode and the second
 	    argument is what function is used to compile the instruction
 	    (some instructions are actually versions of other instructions). """
-	NOP = 0, "_default_render"
-	PUSH = 1, "_default_render", ArgType.VAL
-	POP = 2, "_default_render", ArgType.REG
-	ADD = 3, "_default_render", ArgType.REG, ArgType.VAL, ArgType.VAL
-	MUL = 4, "_default_render", ArgType.REG, ArgType.VAL, ArgType.VAL
-	DIV = 5, "_default_render", ArgType.REG, ArgType.VAL, ArgType.VAL
+	NOP = 0, "_render_default"
+	PUSH = 1, "_render_default", ArgType.VAL
+	POP = 2, "_render_default", ArgType.REG
+	ADD = 3, "_render_default", ArgType.REG, ArgType.VAL, ArgType.VAL
+	MOV = "ADD", "_render_mov", ArgType.REG, ArgType.VAL
+	MUL = 4, "_render_default", ArgType.REG, ArgType.VAL, ArgType.VAL
+	DIV = 5, "_render_default", ArgType.REG, ArgType.VAL, ArgType.VAL
 	SDIV = "DIV", "_render_change_args", ArgType.REG, ArgType.VAL, ArgType.VAL
-	SYS = 6, "_default_render", ArgType.VAL
-	CLB = 7, "_default_render", ArgType.LAB
-	JL = 8, "_default_render", ArgType.LAB, ArgType.VAL, ArgType.VAL
+	SYS = 6, "_render_default", ArgType.VAL
+	CLB = 7, "_render_default", ArgType.LAB
+	JL = 8, "_render_default", ArgType.LAB, ArgType.VAL, ArgType.VAL
 	JLS = "JL", "_render_change_args", ArgType.LAB, ArgType.VAL, ArgType.VAL
-	JLE = 9, "_default_render", ArgType.LAB, ArgType.VAL, ArgType.VAL
+	JLE = 9, "_render_default", ArgType.LAB, ArgType.VAL, ArgType.VAL
 	JLES = "JLE", "_render_change_args", ArgType.LAB, ArgType.VAL, ArgType.VAL
-	JE = 10, "_default_render", ArgType.LAB, ArgType.VAL, ArgType.VAL
-	JNE = 11, "_default_render", ArgType.LAB, ArgType.VAL, ArgType.VAL
+	JE = 10, "_render_default", ArgType.LAB, ArgType.VAL, ArgType.VAL
+	J = "JE", "_render_j", ArgType.LAB
+	JNE = 11, "_render_default", ArgType.LAB, ArgType.VAL, ArgType.VAL
 
 	def __int__(self):
 		""" Returns the opcode associated with the Instruction.
@@ -219,13 +221,22 @@ class Instruction(Enum):
 			rargs.append(t)
 		return rargs
 
+	def _render_mov(self, args):
+		args = [args[0], args[1], Argument(ArgType.IMM, 0)]
+		return Instruction[self.opcode].render(args)
+
+	def _render_j(self, args):
+		args = [args[0], Argument(ArgType.IMM, 0),
+		        Argument(ArgType.IMM, 0)]
+		return Instruction[self.opcode].render(args)
+
 	def _render_change_args(self, args):
 		for i in range(0,len(args)):
 			if args[i].at != ArgType.LAB:
 				args[i].sign = True
 		return Instruction[self.opcode].render(args)
 
-	def _default_render(self, args):
+	def _render_default(self, args):
 		b = bytes([self.opcode])
 		for a in args:
 			l = 2 if a.val < 0x80 else None
diff --git a/asm/test.py b/asm/test.py
index 4008e3d..52ae268 100644
--- a/asm/test.py
+++ b/asm/test.py
@@ -310,6 +310,19 @@ class DivTest(unittest.TestCase):
 		self.assertEqual(cm.exception.opcode, 5)
 
 class LabelTest(unittest.TestCase):
+	def test_unconditional_jump(self):
+		p = Program()
+		p.parse_lines([
+			"mov r0 5",
+			"mov r0 6",
+			"j l0",
+			"mov r0 7",
+			"CLB l0",
+		])
+		ex = ffi.Environment(p())
+		self.assertEqual(ex(), ffi.RunRet.STOP)
+		self.assertEqual(ex.getreg(0), 6)
+
 	def test_simple_loop(self):
 		p = Program()
 		p.parse_lines([
@@ -338,5 +351,14 @@ class ProgramTest(unittest.TestCase):
 		self.assertEqual(ex.getreg(0), 6)
 		self.assertEqual(ex.getreg(1), 5)
 
+	def test_parse_2_byte_num(self):
+		p = Program()
+		p.parse_asm_line("mov r0 127")
+		p.parse_asm_line("mov r1 128")
+		ex = ffi.Environment(p())
+		self.assertEqual(ex(), ffi.RunRet.STOP)
+		self.assertEqual(ex.getreg(0), 127)
+		self.assertEqual(ex.getreg(1), 128)
+
 if __name__ == "__main__":
 	unittest.main()