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more add tests

This commit is contained in:
Peter McGoron 2023-02-11 17:11:32 +00:00
parent 15fb92e502
commit 07347d1f66
2 changed files with 78 additions and 14 deletions
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6
asm/creole.py
View File

@ -83,9 +83,9 @@ class Instruction(Enum):
NOP = 0 NOP = 0
PUSH = 1, ArgType.VAL PUSH = 1, ArgType.VAL
POP = 2, ArgType.REG POP = 2, ArgType.REG
ADD = 3, ArgType.VAL, ArgType.VAL, ArgType.VAL ADD = 3, ArgType.REG, ArgType.VAL, ArgType.VAL
MUL = 4, ArgType.VAL, ArgType.VAL, ArgType.VAL MUL = 4, ArgType.REG, ArgType.VAL, ArgType.VAL
DIV = 5, ArgType.VAL, ArgType.VAL, ArgType.VAL DIV = 5, ArgType.REG, ArgType.VAL, ArgType.VAL
JL = 6, ArgType.LAB, ArgType.VAL, ArgType.VAL JL = 6, ArgType.LAB, ArgType.VAL, ArgType.VAL
CLB = 7, ArgType.LAB CLB = 7, ArgType.LAB
SYS = 8, ArgType.VAL SYS = 8, ArgType.VAL

86
asm/test.py
View File

@ -130,6 +130,81 @@ class PopTest(unittest.TestCase):
self.assertEqual(cm.exception.insargs, []) self.assertEqual(cm.exception.insargs, [])
self.assertEqual(cm.exception.argtypelen, 1) self.assertEqual(cm.exception.argtypelen, 1)
class AddTest(unittest.TestCase):
def test_exec_add(self):
p = Program()
p.parse_asm_line("add r0 1 1")
ex = ffi.Environment()
self.assertEqual(ex.load(p()), ffi.CompileRet.OK)
self.assertEqual(ex(), ffi.RunRet.STOP)
self.assertEqual(ex.cenv.reg[0], 2)
def test_exec_add_neg(self):
p = Program()
p.parse_asm_line("add r0 10 20")
p.parse_asm_line("add r1 5 0")
p.parse_asm_line("add r1 r0 -40")
ex = ffi.Environment()
self.assertEqual(ex.load(p()), ffi.CompileRet.OK)
self.assertEqual(ex(), ffi.RunRet.STOP)
self.assertEqual(ex.cenv.reg[0], 30)
self.assertEqual(ex.cenv.reg[1], word_2c(10))
class AddTest(unittest.TestCase):
def test_exec_mul_throw_imm(self):
p = Program()
with self.assertRaises(TypecheckException) as cm:
p.parse_asm_line("add 5 6 7")
self.assertEqual(cm.exception.argtype, ArgType.REG)
self.assertEqual(cm.exception.sarg, '5')
self.assertEqual(cm.exception.i, 0)
self.assertEqual(cm.exception.opcode, 3)
def test_exec_mul_throw_imm(self):
p = Program()
with self.assertRaises(TypecheckException) as cm:
p.parse_asm_line("add 5 6 7")
self.assertEqual(cm.exception.argtype, ArgType.REG)
self.assertEqual(cm.exception.sarg, '5')
self.assertEqual(cm.exception.i, 0)
self.assertEqual(cm.exception.opcode, 3)
def test_exec_mul_throw_lab_1(self):
p = Program()
with self.assertRaises(TypecheckException) as cm:
p.parse_asm_line("add r0 l6 7")
self.assertEqual(cm.exception.argtype, ArgType.VAL)
self.assertEqual(cm.exception.sarg, 'l6')
self.assertEqual(cm.exception.i, 1)
self.assertEqual(cm.exception.opcode, 3)
def test_exec_mul_throw_lab_2(self):
p = Program()
with self.assertRaises(TypecheckException) as cm:
p.parse_asm_line("add r0 12 l24")
self.assertEqual(cm.exception.argtype, ArgType.VAL)
self.assertEqual(cm.exception.sarg, 'l24')
self.assertEqual(cm.exception.i, 2)
self.assertEqual(cm.exception.opcode, 3)
def test_exec_mul_imm_imm(self):
p = Program()
p.parse_asm_line("mul r0 2 2")
ex = ffi.Environment()
self.assertEqual(ex.load(p()), ffi.CompileRet.OK)
self.assertEqual(ex(), ffi.RunRet.STOP)
self.assertEqual(ex.cenv.reg[0], 4)
def test_exec_mul_imm_neg_imm(self):
p = Program()
p.parse_asm_line("mul r0 -5 5")
p.parse_asm_line("mul r1 r0 -5")
ex = ffi.Environment()
self.assertEqual(ex.load(p()), ffi.CompileRet.OK)
self.assertEqual(ex(), ffi.RunRet.STOP)
self.assertEqual(ex.cenv.reg[0], word_2c(25))
self.assertEqual(ex.cenv.reg[1], 125)
class ProgramTest(unittest.TestCase): class ProgramTest(unittest.TestCase):
def test_exec_simple_reg(self): def test_exec_simple_reg(self):
p = Program() p = Program()
@ -143,16 +218,5 @@ class ProgramTest(unittest.TestCase):
self.assertEqual(ex.cenv.reg[0], 6) self.assertEqual(ex.cenv.reg[0], 6)
self.assertEqual(ex.cenv.reg[1], 5) self.assertEqual(ex.cenv.reg[1], 5)
def test_exec_add(self):
p = Program()
p.parse_asm_line("add r0 10 20")
p.parse_asm_line("add r1 5 0")
p.parse_asm_line("add r1 r0 -40")
ex = ffi.Environment()
self.assertEqual(ex.load(p()), ffi.CompileRet.OK)
self.assertEqual(ex(), ffi.RunRet.STOP)
self.assertEqual(ex.cenv.reg[0], 30)
self.assertEqual(ex.cenv.reg[1], word_2c(10))
if __name__ == "__main__": if __name__ == "__main__":
unittest.main() unittest.main()