add signed division IDIV
This commit is contained in:
parent
18ad8f03c6
commit
5f3275cf2d
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@ -11,6 +11,11 @@ def word_2c(w):
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def ti(w):
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""" Explicitly transform integer into two's compliment representation. """
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return w if w >= 0 else word_wc(-w)
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def from_2c(w):
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""" Turn two's compliment word into Python integer. """
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if (w >> 31) & 1 == 0:
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return w
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return -word_2c(w)
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class ArgType(Enum):
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""" Class denoting the type of an argument to an instruction. """
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@ -86,9 +91,10 @@ class Instruction(Enum):
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ADD = 3, ArgType.REG, ArgType.VAL, ArgType.VAL
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MUL = 4, ArgType.REG, ArgType.VAL, ArgType.VAL
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DIV = 5, ArgType.REG, ArgType.VAL, ArgType.VAL
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JL = 6, ArgType.LAB, ArgType.VAL, ArgType.VAL
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CLB = 7, ArgType.LAB
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SYS = 8, ArgType.VAL
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IDIV = 6, ArgType.REG, ArgType.VAL, ArgType.VAL
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JL = 7, ArgType.LAB, ArgType.VAL, ArgType.VAL
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CLB = 8, ArgType.LAB
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SYS = 9, ArgType.VAL
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def __init__(self, opcode, *args):
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if opcode > 0x7F or opcode < 0:
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32
asm/ffi.py
32
asm/ffi.py
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@ -1,4 +1,5 @@
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from ctypes import *
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import creole
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from enum import Enum
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dll = CDLL("./libcreole.so")
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@ -24,6 +25,7 @@ class RunRet(Enum):
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RUN_LABEL_OVERFLOW = 5
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REGISTER_OVERFLOW = 6
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UNKNOWN_OPCODE = 7
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DIVIDE_BY_ZERO = 8
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def is_halt(self):
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return not (self == RunRet.CONTINUE or self == RunRet.SYSCALL)
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@ -59,8 +61,30 @@ class CEnv(Structure):
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("prglen", c_size_t)
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]
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class RegisterOverflowError(Exception):
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def __init__(self, reg):
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self.reg = reg
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class StackOverflowError(Exception):
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def __init__(self, pos):
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self.pos = pos
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class InvalidSyscallError(Exception):
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def __init__(self, sc):
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self.sc = sc
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class CompileError(Exception):
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def __init__(self, r):
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self.r = r
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class Environment:
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def __init__(self, reglen=32, lablen=32, stklen=4096, prglen=4096):
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def getreg(self, reg):
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if reg >= self.cenv.reglen or reg < 0:
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raise RegisterOverflowError(r)
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return creole.from_2c(self.cenv.reg[reg])
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def getstk(self, stk):
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if stk >= self.cenv.stklen or stk < 0:
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raise StackOverflowError(r)
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return creole.from_2c(self.cenv.stk[stk])
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def __init__(self, prog=None, reglen=32, lablen=32, stklen=4096, prglen=4096):
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cenv = CEnv()
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cenv.reglen = reglen
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cenv.reg = (c_uint * reglen)()
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@ -78,6 +102,10 @@ class Environment:
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cenv.prgend = 0
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self.cenv = cenv
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if prog is not None:
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r = self.load(prog)
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if r is not CompileRet.OK:
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raise CompileError(r)
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def restart(self):
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self.cenv.stkptr = 0
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@ -91,7 +119,7 @@ class Environment:
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return CompileRet(ret)
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def syscall(self, sc):
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pass
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raise InvalidSyscallError(sc)
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def __call__(self):
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sc = c_size_t()
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ret = RunRet.CONTINUE
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109
asm/test.py
109
asm/test.py
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@ -56,10 +56,8 @@ class PushTest(unittest.TestCase):
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p = Program()
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p.parse_asm_line("PUSH r0")
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p.parse_asm_line("PUSH 6")
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b = p()
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ex = ffi.Environment()
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self.assertEqual(ex.load(b), ffi.CompileRet.OK)
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ex = ffi.Environment(p())
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self.assertEqual(ex.cenv.prgend, 2)
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self.assertEqual(ex.cenv.prg[0].opcode, 1)
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@ -83,19 +81,17 @@ class PushTest(unittest.TestCase):
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stklen = 40
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for n in range(0,stklen):
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p.parse_asm_line("PUSH 5")
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ex = ffi.Environment(stklen=stklen)
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self.assertEqual(ex.load(p()), ffi.CompileRet.OK)
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ex = ffi.Environment(p(), stklen=stklen)
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self.assertEqual(ex(), ffi.RunRet.STOP)
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for n in range(0,stklen):
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self.assertEqual(ex.cenv.stk[n], 5)
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self.assertEqual(ex.getstk(n), 5)
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def test_push_overflow(self):
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p = Program()
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stklen = 40
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for n in range(0, stklen + 1):
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p.parse_asm_line("PUSH 5")
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ex = ffi.Environment(stklen=stklen)
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self.assertEqual(ex.load(p()), ffi.CompileRet.OK)
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ex = ffi.Environment(p(), stklen=stklen)
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self.assertEqual(ex(), ffi.RunRet.STACK_OVERFLOW)
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class PopTest(unittest.TestCase):
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@ -104,8 +100,7 @@ class PopTest(unittest.TestCase):
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p.parse_asm_line("pop r9")
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b = p()
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self.assertEqual(b, b'\x02\xC2\x89\x00')
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ex = ffi.Environment()
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self.assertEqual(ex.load(b), ffi.CompileRet.OK)
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ex = ffi.Environment(b)
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self.assertEqual(ex.cenv.prgend, 1)
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self.assertEqual(ex.cenv.prg[0].opcode, 2)
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@ -152,8 +147,7 @@ class PopTest(unittest.TestCase):
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def test_pop_underflow(self):
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p = Program()
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p.parse_asm_line("pop r0")
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ex = ffi.Environment()
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self.assertEqual(ex.load(p()), ffi.CompileRet.OK)
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ex = ffi.Environment(p())
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self.assertEqual(ex(), ffi.RunRet.STACK_UNDERFLOW)
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def test_pop_underflow_2(self):
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@ -161,16 +155,14 @@ class PopTest(unittest.TestCase):
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p.parse_asm_line("push 5")
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p.parse_asm_line("pop r0")
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p.parse_asm_line("pop r1")
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ex = ffi.Environment()
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self.assertEqual(ex.load(p()), ffi.CompileRet.OK)
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ex = ffi.Environment(p())
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self.assertEqual(ex(), ffi.RunRet.STACK_UNDERFLOW)
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class AddTest(unittest.TestCase):
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def test_exec_add(self):
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p = Program()
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p.parse_asm_line("add r0 1 1")
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ex = ffi.Environment()
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self.assertEqual(ex.load(p()), ffi.CompileRet.OK)
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ex = ffi.Environment(p())
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self.assertEqual(ex(), ffi.RunRet.STOP)
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self.assertEqual(ex.cenv.reg[0], 2)
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@ -179,11 +171,10 @@ class AddTest(unittest.TestCase):
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p.parse_asm_line("add r0 10 20")
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p.parse_asm_line("add r1 5 0")
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p.parse_asm_line("add r1 r0 -40")
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ex = ffi.Environment()
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self.assertEqual(ex.load(p()), ffi.CompileRet.OK)
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ex = ffi.Environment(p())
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self.assertEqual(ex(), ffi.RunRet.STOP)
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self.assertEqual(ex.cenv.reg[0], 30)
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self.assertEqual(ex.cenv.reg[1], word_2c(10))
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self.assertEqual(ex.getreg(0), 30)
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self.assertEqual(ex.getreg(1), -10)
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def test_exec_add_throw_imm(self):
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p = Program()
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@ -216,20 +207,18 @@ class MulTest(unittest.TestCase):
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def test_exec_mul_imm_imm(self):
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p = Program()
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p.parse_asm_line("mul r0 2 2")
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ex = ffi.Environment()
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self.assertEqual(ex.load(p()), ffi.CompileRet.OK)
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ex = ffi.Environment(p())
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self.assertEqual(ex(), ffi.RunRet.STOP)
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self.assertEqual(ex.cenv.reg[0], 4)
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self.assertEqual(ex.getreg(0), 4)
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def test_exec_mul_imm_neg_imm(self):
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p = Program()
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p.parse_asm_line("mul r0 -5 5")
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p.parse_asm_line("mul r1 r0 -5")
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ex = ffi.Environment()
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self.assertEqual(ex.load(p()), ffi.CompileRet.OK)
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ex = ffi.Environment(p())
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self.assertEqual(ex(), ffi.RunRet.STOP)
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self.assertEqual(ex.cenv.reg[0], word_2c(25))
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self.assertEqual(ex.cenv.reg[1], 125)
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self.assertEqual(ex.getreg(0), -25)
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self.assertEqual(ex.getreg(1), 125)
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def test_exec_mul_throw_imm(self):
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p = Program()
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@ -258,6 +247,68 @@ class MulTest(unittest.TestCase):
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self.assertEqual(cm.exception.i, 2)
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self.assertEqual(cm.exception.opcode, 4)
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class DivTest(unittest.TestCase):
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def test_div(self):
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p = Program()
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p.parse_asm_line("div r0 8 4")
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ex = ffi.Environment(p())
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self.assertEqual(ex(), ffi.RunRet.STOP)
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self.assertEqual(ex.getreg(0), 2)
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def test_div_round_down(self):
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p = Program()
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p.parse_asm_line("div r0 8 10")
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ex = ffi.Environment(p())
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self.assertEqual(ex(), ffi.RunRet.STOP)
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def test_div_by_zero(self):
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p = Program()
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p.parse_asm_line("div r0 8 0")
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ex = ffi.Environment(p())
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self.assertEqual(ex(), ffi.RunRet.DIVIDE_BY_ZERO)
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def test_idiv_by_zero(self):
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p = Program()
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p.parse_asm_line("idiv r0 8 0")
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ex = ffi.Environment(p())
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self.assertEqual(ex(), ffi.RunRet.DIVIDE_BY_ZERO)
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def test_div_neg(self):
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p = Program()
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p.parse_asm_line("idiv r0 16 -4")
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p.parse_asm_line("idiv r1 r0 -4")
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ex = ffi.Environment(p())
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self.assertEqual(ex(), ffi.RunRet.STOP)
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self.assertEqual(ex.getreg(0), -4)
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self.assertEqual(ex.getreg(1), 1)
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def test_exec_div_throw_imm(self):
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p = Program()
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with self.assertRaises(TypecheckException) as cm:
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p.parse_asm_line("div 5 1 2")
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self.assertEqual(cm.exception.argtype, ArgType.REG)
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self.assertEqual(cm.exception.sarg, '5')
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self.assertEqual(cm.exception.i, 0)
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self.assertEqual(cm.exception.opcode, 5)
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def test_exec_div_throw_lab_1(self):
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p = Program()
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with self.assertRaises(TypecheckException) as cm:
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p.parse_asm_line("div r0 l123 456")
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self.assertEqual(cm.exception.argtype, ArgType.VAL)
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self.assertEqual(cm.exception.sarg, 'l123')
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self.assertEqual(cm.exception.i, 1)
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self.assertEqual(cm.exception.opcode, 5)
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def test_exec_div_throw_lab_2(self):
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p = Program()
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with self.assertRaises(TypecheckException) as cm:
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p.parse_asm_line("div r5 1919 l24")
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self.assertEqual(cm.exception.argtype, ArgType.VAL)
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self.assertEqual(cm.exception.sarg, 'l24')
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self.assertEqual(cm.exception.i, 2)
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self.assertEqual(cm.exception.opcode, 5)
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class ProgramTest(unittest.TestCase):
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def test_exec_simple_reg(self):
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p = Program()
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@ -268,8 +319,8 @@ class ProgramTest(unittest.TestCase):
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ex = ffi.Environment()
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self.assertEqual(ex.load(p()), ffi.CompileRet.OK)
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self.assertEqual(ex(), ffi.RunRet.STOP)
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self.assertEqual(ex.cenv.reg[0], 6)
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self.assertEqual(ex.cenv.reg[1], 5)
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self.assertEqual(ex.getreg(0), 6)
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self.assertEqual(ex.getreg(1), 5)
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if __name__ == "__main__":
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unittest.main()
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14
creole.c
14
creole.c
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@ -35,6 +35,7 @@ static const struct {
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defop(ADD, 3, TYPE_REG, TYPE_VAL, TYPE_VAL),
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defop(MUL, 3, TYPE_REG, TYPE_VAL, TYPE_VAL),
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defop(DIV, 3, TYPE_REG, TYPE_VAL, TYPE_VAL),
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defop(IDIV, 3, TYPE_REG, TYPE_VAL, TYPE_VAL),
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defop(JL, 3, TYPE_LAB, TYPE_VAL, TYPE_VAL),
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defop(CLB, 1, TYPE_LAB, TYPE_NONE, TYPE_NONE),
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defop(SYS, 1, TYPE_VAL, TYPE_NONE, TYPE_NONE)
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@ -323,8 +324,9 @@ creole_parse_line(struct creole_ins *ins, struct creole_reader *r)
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return CREOLE_OPCODE_READ_ERROR;
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ins->opcode = w.word;
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if (w.word >= CREOLE_ARG_TYPE_LEN || w.len != 1)
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if (w.word >= CREOLE_OPCODE_LEN || w.len != 1) {
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return CREOLE_OPCODE_MALFORMED;
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}
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for (arg = 0; arg < opcode_info[ins->opcode].arglen; arg++) {
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if (!decode_seq(r, &w))
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@ -542,8 +544,18 @@ enum creole_run_ret creole_step(struct creole_env *env, creole_word *sc)
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case CREOLE_DIV:
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check(read_val(env, ins, 1, &a1));
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check(read_val(env, ins, 2, &a2));
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if (a2 == 0)
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return CREOLE_DIV_BY_ZERO;
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check(creole_reg_write(env, ins->w[0], a1 / a2));
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break;
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case CREOLE_IDIV:
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check(read_val(env, ins, 1, &a1));
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check(read_val(env, ins, 2, &a2));
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if (a2 == 0)
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return CREOLE_DIV_BY_ZERO;
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check(creole_reg_write(env, ins->w[0],
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(creole_signed)a1 / (creole_signed)a2));
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break;
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case CREOLE_JL:
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check(read_val(env, ins, 1, &a1));
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check(read_val(env, ins, 2, &a2));
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11
creole.h
11
creole.h
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@ -7,11 +7,14 @@
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#ifndef CREOLE_WORD
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# define CREOLE_WORD unsigned int
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# define CREOLE_WORD_MAX UINT_MAX
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# define CREOLE_SIGNED_WORD int
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# define CREOLE_SIGNED_MAX INT_MAX
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#endif
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#define CREOLE_MAX_ARG 3
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typedef CREOLE_WORD creole_word;
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typedef CREOLE_SIGNED_WORD creole_signed;
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enum creole_opcode {
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CREOLE_NOOP = 0,
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@ -20,9 +23,10 @@ enum creole_opcode {
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CREOLE_ADD = 3,
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CREOLE_MUL = 4,
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CREOLE_DIV = 5,
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CREOLE_JL = 6,
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CREOLE_CLB = 7,
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CREOLE_SYS = 8,
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CREOLE_IDIV = 6,
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CREOLE_JL = 7,
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CREOLE_CLB = 8,
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CREOLE_SYS = 9,
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CREOLE_OPCODE_LEN
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};
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@ -56,6 +60,7 @@ enum creole_run_ret {
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CREOLE_RUN_LABEL_OVERFLOW,
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CREOLE_REGISTER_OVERFLOW,
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CREOLE_STEP_UNKNOWN_OPCODE,
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CREOLE_DIV_BY_ZERO,
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CREOLE_RUN_RET_LEN
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};
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