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add immediate signed and unsigned tests

This commit is contained in:
Peter McGoron 2023-02-12 19:52:41 +00:00
parent 00e9d12c71
commit 827abe4305
2 changed files with 48 additions and 13 deletions
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19
asm/ffi.py
View File

@ -76,11 +76,26 @@ class CompileError(Exception):
self.r = r self.r = r
class Environment: class Environment:
def getreg(self, reg): def getreg(self, reg, signed=False):
""" Get the value at the register.
:param reg: Register number.
:param signed: If the register value should be interpreted
as signed.
"""
if reg >= self.cenv.reglen or reg < 0: if reg >= self.cenv.reglen or reg < 0:
raise RegisterOverflowError(r) raise RegisterOverflowError(r)
return creole.from_2c(self.cenv.reg[reg]) if signed:
return creole.from_2c(self.cenv.reg[reg])
else:
return self.cenv.reg[reg]
def getstk(self, stk): def getstk(self, stk):
""" Get the value at the stack position.
:param reg: Register number.
:param signed: If the stack value should be interpreted
as signed.
"""
if stk >= self.cenv.stklen or stk < 0: if stk >= self.cenv.stklen or stk < 0:
raise StackOverflowError(r) raise StackOverflowError(r)
return creole.from_2c(self.cenv.stk[stk]) return creole.from_2c(self.cenv.stk[stk])

42
asm/test.py
View File

@ -174,7 +174,7 @@ class AddTest(unittest.TestCase):
ex = ffi.Environment(p()) ex = ffi.Environment(p())
self.assertEqual(ex(), ffi.RunRet.STOP) self.assertEqual(ex(), ffi.RunRet.STOP)
self.assertEqual(ex.getreg(0), 30) self.assertEqual(ex.getreg(0), 30)
self.assertEqual(ex.getreg(1), -10) self.assertEqual(ex.getreg(1, signed=True), -10)
def test_exec_add_throw_imm(self): def test_exec_add_throw_imm(self):
p = Program() p = Program()
@ -217,7 +217,7 @@ class MulTest(unittest.TestCase):
p.parse_asm_line("mul r1 r0 -5") p.parse_asm_line("mul r1 r0 -5")
ex = ffi.Environment(p()) ex = ffi.Environment(p())
self.assertEqual(ex(), ffi.RunRet.STOP) self.assertEqual(ex(), ffi.RunRet.STOP)
self.assertEqual(ex.getreg(0), -25) self.assertEqual(ex.getreg(0, signed=True), -25)
self.assertEqual(ex.getreg(1), 125) self.assertEqual(ex.getreg(1), 125)
def test_exec_mul_throw_imm(self): def test_exec_mul_throw_imm(self):
@ -279,7 +279,7 @@ class DivTest(unittest.TestCase):
p.parse_asm_line("sdiv r1 r0 -4") p.parse_asm_line("sdiv r1 r0 -4")
ex = ffi.Environment(p()) ex = ffi.Environment(p())
self.assertEqual(ex(), ffi.RunRet.STOP) self.assertEqual(ex(), ffi.RunRet.STOP)
self.assertEqual(ex.getreg(0), -4) self.assertEqual(ex.getreg(0, signed=True), -4)
self.assertEqual(ex.getreg(1), 1) self.assertEqual(ex.getreg(1), 1)
def test_exec_div_throw_imm(self): def test_exec_div_throw_imm(self):
@ -351,14 +351,34 @@ class ProgramTest(unittest.TestCase):
self.assertEqual(ex.getreg(0), 6) self.assertEqual(ex.getreg(0), 6)
self.assertEqual(ex.getreg(1), 5) self.assertEqual(ex.getreg(1), 5)
def test_parse_2_byte_num(self): def range_test(self, st, en, sgn=False):
p = Program() for i in range(st, en):
p.parse_asm_line("mov r0 127") p = Program()
p.parse_asm_line("mov r1 128") p.parse_asm_line(f"mov r0 {i}")
ex = ffi.Environment(p()) ex = ffi.Environment(p())
self.assertEqual(ex(), ffi.RunRet.STOP) self.assertEqual(ex(), ffi.RunRet.STOP)
self.assertEqual(ex.getreg(0), 127) self.assertEqual(ex.getreg(0, signed=sgn), i)
self.assertEqual(ex.getreg(1), 128)
def test_parse_imm_compile(self):
self.range_test(0, 0x1000)
self.range_test(0x1000, 0x1100)
self.range_test(0x1FF00, 0x20000)
self.range_test(0x20000, 0x20100)
self.range_test(0x3FFF00, 0x400000)
self.range_test(0x400000, 0x400100)
self.range_test(0x7FFFF00, 0x8000000)
self.range_test(0x8000000, 0x8000100)
self.range_test(0xFFFFFF00, 0x100000000)
def test_parse_imm_signed(self):
self.range_test(0, 0x1000, sgn=True)
self.range_test(0x1000, 0x1100, sgn=True)
self.range_test(0x1FF00, 0x20000, sgn=True)
self.range_test(0x20000, 0x20100, sgn=True)
self.range_test(0x3FFF00, 0x400000, sgn=True)
self.range_test(0x400000, 0x400100, sgn=True)
self.range_test(0x7FFFF00, 0x8000000, sgn=True)
self.range_test(-100, 0, sgn=True)
if __name__ == "__main__": if __name__ == "__main__":
unittest.main() unittest.main()