spi/tests/simtop.v

/* (c) Peter McGoron 2022
 * This Source Code Form is subject to the terms of the Mozilla Public
 * License, v.2.0. If a copy of the MPL was not distributed with this
 * file, You can obtain one at https://mozilla.org/MPL/2.0/.
 */

module simtop
#(
	parameter POLARITY = 0,
	parameter PHASE = 0,
	parameter WID = 24,
	parameter WID_LEN = 5
) (
	input clk,
`ifndef SPI_MASTER_NO_WRITE
	input [WID-1:0] master_to_slave,
	output [WID-1:0] from_master,
`endif
`ifndef SPI_MASTER_NO_READ
	input [WID-1:0] slave_to_master,
	output [WID-1:0] from_slave,
`endif
	input activate,
`ifndef SPI_MASTER_SS
	input ss,
`endif
	input rdy,
	output master_finished,
	output ready_to_arm,
	output err
);

`ifndef SPI_MASTER_NO_READ
wire miso;
`endif

`ifndef SPI_MASTER_NO_WRITE
wire mosi;
`endif

wire sck;
wire ss_L;

`ifndef SPI_MASTER_SS
assign ss_L = !ss;
`endif

reg slave_finished;
reg slave_error;

`SPI_MASTER_TYPE
#(
`ifdef SPI_MASTER_SS
	.SS_WAIT(5),
	.SS_WAIT_TIMER_LEN(3),
`endif
	.CYCLE_HALF_WAIT(5),
	.TIMER_LEN(3),
	.POLARITY(POLARITY),
	.PHASE(PHASE),
	.WID(WID),
	.WID_LEN(WID_LEN)
) master (
	.clk(clk),
`ifndef SPI_MASTER_NO_WRITE
	.to_slave(master_to_slave),
	.mosi(mosi),
`endif
`ifndef SPI_MASTER_NO_READ
	.from_slave(from_slave),
	.miso(miso),
`endif
`ifdef SPI_MASTER_SS
	.ss_L(ss_L),
`endif
	.sck_wire(sck),
	.finished(master_finished),
	.ready_to_arm(ready_to_arm),
	.arm(activate)
);

`SPI_SLAVE_TYPE #(
	.POLARITY(POLARITY),
	.PHASE(PHASE),
	.WID(WID),
	.WID_LEN(WID_LEN)
) slave (
	.clk(clk),
	.sck(sck),
	.ss_L(ss_L),
`ifndef SPI_MASTER_NO_WRITE
	.from_master(from_master),
	.mosi(mosi),
`endif
`ifndef SPI_MASTER_NO_READ
	.to_master(slave_to_master),
	.miso(miso),
`endif
	.finished(slave_finished),
	.rdy(rdy),
	.err(err)
);

`ifdef SIMULATION
initial begin
	$dumpfile(`VCDFILE);
	$dumpvars;
end
`endif

endmodule