108 lines
2.1 KiB
Coq
108 lines
2.1 KiB
Coq
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/* (c) Peter McGoron 2022 v0.4
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*
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* This code is disjunctively dual-licensed under the MPL v2.0, or the
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* CERN-OHL-W v2.
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*/
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module spi_master_ss
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#(
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parameter BUS_WID = 32, /* Width of a request on the bus. */
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parameter SELECT_WID = 4, /* Width of the wishbone byte select. */
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parameter SS_WAIT = 1,
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parameter SS_WAIT_TIMER_LEN = 2,
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parameter ENABLE_MISO = 1,
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parameter ENABLE_MOSI = 1,
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parameter WID = 24,
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parameter WID_LEN = 5,
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parameter CYCLE_HALF_WAIT = 1,
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parameter TIMER_LEN = 3,
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parameter POLARITY = 0,
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parameter PHASE = 0
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) (
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input clk,
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input rst_L,
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input miso,
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output reg mosi,
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output sck_wire,
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output ss_L
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input wb_cyc,
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input wb_stb,
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input wb_we,
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input [SELECT_WID-1:0] wb_sel,
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input [BUS_WID-1:0] wb_addr,
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input [BUS_WID-1:0] wb_dat_w,
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output reg wb_ack,
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output reg [BUS_WID-1:0] wb_dat_r,
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);
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/* Address map:
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All words are little endian. Access must be word-aligned and word-level
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or undefined behavior will occur.
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word 0: ready_to_arm | (finished << 1) (RW)
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word 1: arm (RO)
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word 2: from_slave (RO)
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word 3: to_slave (RW)
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*/
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wire [WID-1:0] from_slave;
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reg [WID-1:0] to_slave;
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wire finished;
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wire ready_to_arm;
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reg arm;
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spi_master_ss #(
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.SS_WAIT(SS_WAIT),
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.SS_WAIT_TIMER_LEN(SS_WAIT_TIMER_LEN),
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.ENABLE_MISO(ENABLE_MISO),
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.ENABLE_MOSI(ENABLE_MOSI),
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.WID(WID),
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.WID_LEN(WID_LEN),
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.CYCLE_HALF_WAIT(CYCLE_HALF_WAIT),
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.TIMER_LEN(TIMER_LEN),
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.POLARITY(POLARITY),
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.PHASE(PHASE)
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) spi (
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.clk(clk),
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.rst_L(rst_L),
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.from_slave(from_slave),
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.miso(miso),
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.to_slave(to_slave),
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.mosi(mosi),
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.sck_wire(sck_wire),
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.finished(finished),
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.ready_to_arm(ready_to_arm),
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.ss_L(ss_L),
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.arm(arm)
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);
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always @ (posedge clk) if (wb_cyc && wb_stb && !wb_ack) begin
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if (!wb_we) case (wb_addr[4-1:0])
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4'h0: wb_dat_r <= {30'b0, finished, ready_to_arm};
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4'h4: wb_dat_r <= {31'b0, arm};
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4'h8: wb_dat_r <= from_slave;
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4'hC: wb_dat_r <= to_slave;
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default: wb_dat_r <= 0;
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endcase else case (wb_addr[4-1:0])
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4'h4: arm <= wb_dat_w[0];
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4'hC: to_slave <= wb_dat_w;
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default: ;
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end
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wb_ack <= 1;
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end else begin
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wb_ack <= 0;
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end
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endmodule
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