2022-07-21 03:18:22 -04:00
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# Verilog SPI
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Verilog SPI master and slave that supports all modes and variable width
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via parameters.
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## License
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2022-10-22 18:34:54 -04:00
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All code in this project is licensed to the terms of the Mozilla Public
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License, v.2.0. A copy of this license may be found in the file `COPYING`. You
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2022-07-21 03:18:22 -04:00
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can obtain one at https://mozilla.org/MPL/2.0/.
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2022-07-21 11:10:36 -04:00
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2022-10-22 18:34:54 -04:00
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All Verilog source in this project is dual-licensed under the MPL v2.0
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and the CERN-OHL-W v2.0 (or any later version).
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2022-07-21 11:10:36 -04:00
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## Tests
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Go into `tests` and run `make`. To rerun tests, run `make clean` followed
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by `make`.
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The test for each mode generates a `.vcd` file which you may view using
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[GTKWave][1]. You can use this to gauge which SPI mode is appropriate for
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your device.
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[1]: https://gtkwave.sourceforge.net/
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## SPI Modes
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Modes are denoted by `modePH`, where `P` is the polarity (0 for normal,
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1 for inverted) and `H` for phase:
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* `H = 0` means the device reads on a rising edge and writes on a falling
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edge.
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* `H = 1` means the device reads on a falling edge and writes on a rising
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edge.
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Although these modules support all SPI modes, they are labeled slightly
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differently from other SPI modes. The phase factor is denoted in terms
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of falling and rising edges, not in terms of leading and trailing edges.
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This means that polarity also flips the phase term, so a mode 3 device
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is a mode 10 device. Devices with regular clock polarity are unaffected,
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so a mode 0 device is a mode 00 device, and a mode 1 device is a mode
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01 device.
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