From 039507d13ab003ad432eb903224dcf7242cc9c23 Mon Sep 17 00:00:00 2001 From: Peter McGoron Date: Sun, 23 Oct 2022 12:37:07 -0400 Subject: [PATCH] test master with SS --- spi_master_ss_template.v | 9 ++++-- tests/mk.sh | 62 +++++++++++++++++++++++++++++----------- tests/simtop.v | 27 +++++++++++++++-- tests/write_read.cpp | 15 ++++++++-- 4 files changed, 87 insertions(+), 26 deletions(-) diff --git a/spi_master_ss_template.v b/spi_master_ss_template.v index 27a4b85..e2e0cc4 100644 --- a/spi_master_ss_template.v +++ b/spi_master_ss_template.v @@ -7,7 +7,7 @@ module `SPI_MASTER_SS_NAME parameter WID = 24, parameter WID_LEN = 5, parameter CYCLE_HALF_WAIT = 1, - parameter CYCLE_HALF_WAIT_TIMER_LEN = 3, + parameter TIMER_LEN = 3, parameter SS_WAIT = 1, parameter SS_WAIT_TIMER_LEN = 2, @@ -33,13 +33,13 @@ module `SPI_MASTER_SS_NAME reg ss = 0; reg arm_master = 0; -assign ss_L = ss; +assign ss_L = !ss; `SPI_MASTER_NAME #( .WID(WID), .WID_LEN(WID_LEN), .CYCLE_HALF_WAIT(CYCLE_HALF_WAIT), - .TIMER_LEN(CYCLE_HALF_WAIT_TIMER_LEN), + .TIMER_LEN(TIMER_LEN), .POLARITY(POLARITY), .PHASE(PHASE) ) master ( @@ -62,6 +62,7 @@ localparam WAIT_ON_SS = 1; localparam WAIT_ON_MASTER = 2; localparam WAIT_ON_ARM_DEASSERT = 3; reg [2:0] state = WAIT_ON_ARM; +reg [SS_WAIT_TIMER_LEN-1:0] timer = 0; task master_arm(); arm_master <= 1; @@ -92,6 +93,7 @@ always @ (posedge clk) begin WAIT_ON_MASTER: begin if (finished) begin state <= WAIT_ON_ARM_DEASSERT; + ss <= 0; end end WAIT_ON_ARM_DEASSERT: begin @@ -100,6 +102,7 @@ always @ (posedge clk) begin arm_master <= 0; end end + endcase end endmodule diff --git a/tests/mk.sh b/tests/mk.sh index 51a9775..99a2949 100755 --- a/tests/mk.sh +++ b/tests/mk.sh @@ -11,12 +11,14 @@ run_test() { EXTARG=$8 WIDLEN=$(printf "import math\nprint(math.floor(math.log2($WID) + 1))" | python3 -) - verilator --cc --exe -I.. -Wall -Wno-unused --trace \ + echo "running $POL$PHASE $MASTER_TYPE" + + verilator --cc --exe -I.. -Wall -Wno-unused --trace --trace-fst \ --top-module simtop \ -GPOLARITY=$POL -GPHASE=$PHASE -GWID=$WID -CFLAGS -DWID=$WID \ -GWID_LEN=$WIDLEN \ -DSPI_MASTER_TYPE=$MASTER_TYPE -DSPI_SLAVE_TYPE=$SLAVE_TYPE \ - -DVCDFILE="\"$DIR.vcd\"" \ + -DVCDFILE="\"$DIR.fst\"" \ --Mdir $DIR \ $EXTARG \ simtop.v write_read.cpp $MODS @@ -35,21 +37,47 @@ for POL in 0 1; do "../spi_master.v ../spi_slave.v" ) -# ( \ -# run_test $POL $PHASE \ -# spi_master_no_write spi_slave_no_read \ -# simtop_no_write_$POL$PHASE 24 \ -# "../spi_master_no_write.v ../spi_slave_no_read.v" \ -# "-DSPI_MASTER_NO_WRITE -CFLAGS -DSPI_MASTER_NO_WRITE" -# ) -# -# ( \ -# run_test $POL $PHASE \ -# spi_master_no_read spi_slave_no_write \ -# simtop_no_read_$POL$PHASE 24 \ -# "../spi_master_no_read.v ../spi_slave_no_write.v" \ -# "-DSPI_MASTER_NO_READ -CFLAGS -DSPI_MASTER_NO_READ" -# ) + ( \ + run_test $POL $PHASE \ + spi_master_ss spi_slave \ + simtop_ss$POL$PHASE 24 \ + "../spi_master_ss.v ../spi_slave.v" \ + "-DSPI_MASTER_SS -CFLAGS -DSPI_MASTER_SS" + ) + + ( \ + run_test $POL $PHASE \ + spi_master_no_write spi_slave_no_read \ + simtop_no_write_$POL$PHASE 24 \ + "../spi_master_no_write.v ../spi_slave_no_read.v" \ + "-DSPI_MASTER_NO_WRITE -CFLAGS -DSPI_MASTER_NO_WRITE" + ) + + ( \ + run_test $POL $PHASE \ + spi_master_ss_no_write spi_slave_no_read \ + simtop_ss_no_write_$POL$PHASE 24 \ + "../spi_master_ss_no_write.v ../spi_slave_no_read.v" \ + "-DSPI_MASTER_NO_WRITE -CFLAGS -DSPI_MASTER_NO_WRITE + -DSPI_MASTER_SS -CFLAGS -DSPI_MASTER_SS" + ) + + ( \ + run_test $POL $PHASE \ + spi_master_no_read spi_slave_no_write \ + simtop_no_read_$POL$PHASE 24 \ + "../spi_master_no_read.v ../spi_slave_no_write.v" \ + "-DSPI_MASTER_NO_READ -CFLAGS -DSPI_MASTER_NO_READ" + ) + + ( \ + run_test $POL $PHASE \ + spi_master_ss_no_read spi_slave_no_write \ + simtop_ss_no_read_$POL$PHASE 24 \ + "../spi_master_ss_no_read.v ../spi_slave_no_write.v" \ + "-DSPI_MASTER_NO_READ -CFLAGS -DSPI_MASTER_NO_READ + -DSPI_MASTER_SS -CFLAGS -DSPI_MASTER_SS" + ) done done diff --git a/tests/simtop.v b/tests/simtop.v index d47a802..a1461bc 100644 --- a/tests/simtop.v +++ b/tests/simtop.v @@ -21,7 +21,9 @@ module simtop output [WID-1:0] from_slave, `endif input activate, +`ifndef SPI_MASTER_SS input ss, +`endif input rdy, output master_finished, output err @@ -36,18 +38,27 @@ wire mosi; `endif wire sck; -wire ss_L = !ss; +wire ss_L; + +`ifndef SPI_MASTER_SS +assign ss_L = !ss; +`endif reg slave_finished; reg slave_error; `SPI_MASTER_TYPE #( +`ifdef SPI_MASTER_SS + .SS_WAIT(5), + .SS_WAIT_TIMER_LEN(3), +`endif + .CYCLE_HALF_WAIT(5), + .TIMER_LEN(3), .POLARITY(POLARITY), .PHASE(PHASE), .WID(WID), - .WID_LEN(WID_LEN), - .CYCLE_HALF_WAIT(5) + .WID_LEN(WID_LEN) ) master ( .clk(clk), `ifndef SPI_MASTER_NO_WRITE @@ -57,6 +68,9 @@ reg slave_error; `ifndef SPI_MASTER_NO_READ .from_slave(from_slave), .miso(miso), +`endif +`ifdef SPI_MASTER_SS + .ss_L(ss_L), `endif .sck_wire(sck), .finished(master_finished), @@ -85,4 +99,11 @@ reg slave_error; .err(err) ); +/* +initial begin + $dumpfile(`VCDFILE); + $dumpvars; +end +*/ + endmodule diff --git a/tests/write_read.cpp b/tests/write_read.cpp index 2394b63..387b58a 100644 --- a/tests/write_read.cpp +++ b/tests/write_read.cpp @@ -4,6 +4,12 @@ Vsimtop *sim; +#ifdef SPI_MASTER_SS +# define SET_SS(mod, v) +#else +# define SET_SS(mod,v) ((mod)->ss = (v)) +#endif + uint32_t main_time = 0; double sc_time_stamp() { @@ -33,7 +39,7 @@ static void test_cross_transfer(unsigned m2s, unsigned s2m) { #endif progress(); - sim->ss = 1; + SET_SS(sim, 1); sim->rdy = 1; sim->activate = 1; progress(); @@ -43,7 +49,7 @@ static void test_cross_transfer(unsigned m2s, unsigned s2m) { progress_n(5); sim->activate = 0; - sim->ss = 0; + SET_SS(sim, 0); sim->rdy = 0; progress_n(5); @@ -73,11 +79,14 @@ int main(int argc, char **argv) { Verilated::traceEverOn(true); sim = new Vsimtop; - sim->ss = 0; + SET_SS(sim, 0); sim->clk = 0; sim->activate = 0; sim->rdy = 0; + test_cross_transfer(0b101010101010101010101010, 0b010101010101010101010101); + test_cross_transfer(0b110011001100110011001100, 0b001100110011001100110011); + for (int i = 0; i < 10000; i++) { unsigned m2s = rand() & ((1 << WID) - 1); unsigned s2m = rand() & ((1 << WID) - 1);