diff --git a/spi_master.v b/spi_master.v
index baf2f5e..f3e67a1 100644
--- a/spi_master.v
+++ b/spi_master.v
@@ -65,6 +65,23 @@ task write_data();
 `endif
 endtask
 
+task setup_bits();
+	/* at Mode 00, the transmission starts with
+	 * a rising edge, and at mode 11, it starts with a falling
+	 * edge. For both modes, these are READs.
+	 *
+	 * For mode 01 and mode 10, the first action is a WRITE.
+	 */
+	if (POLARITY == PHASE) begin
+		mosi <= to_slave[WID-1];
+		send_buf <= to_slave << 1;
+		state <= CYCLE_WAIT;
+	end else begin
+		send_buf <= to_slave;
+		state <= ON_CYCLE;
+	end
+endtask
+
 always @ (posedge clk) begin
 	case (state)
 	WAIT_ON_ARM: begin
@@ -72,22 +89,7 @@ always @ (posedge clk) begin
 			idle_state();
 			finished <= 0;
 		end else begin
-			/* at Mode 00, the transmission starts with
-			 * a rising edge, and at mode 11, it starts
-			 * with a falling edge. For both modes,
-			 * these are READs.
-			 *
-			 * For mode 01 and mode 10, the first
-			 * action is a WRITE.
-			 */
-			if (POLARITY == PHASE) begin
-				mosi <= to_slave[WID-1];
-				send_buf <= to_slave << 1;
-				state <= CYCLE_WAIT;
-			end else begin
-				send_buf <= to_slave;
-				state <= ON_CYCLE;
-			end
+			setup_bits();
 		end
 	end
 	ON_CYCLE: begin
diff --git a/spi_slave.v b/spi_slave.v
index ec397fb..8efce47 100644
--- a/spi_slave.v
+++ b/spi_slave.v
@@ -44,6 +44,21 @@ task write_data();
 `endif
 endtask
 
+task setup_bits();
+	/* at Mode 00, the transmission starts with
+	 * a rising edge, and at mode 11, it starts with a falling
+	 * edge. For both modes, these are READs.
+	 *
+	 * For mode 01 and mode 10, the first action is a WRITE.
+	 */
+	if (POLARITY == PHASE) begin
+		miso <= to_master[WID-1];
+		send_buf <= to_master << 1;
+	end else begin
+		send_buf <= to_master;
+	end
+endtask
+
 always @ (posedge clk) begin
 	sck_delay <= sck;
 	ss_delay <= ss;
@@ -53,6 +68,8 @@ always @ (posedge clk) begin
 		bit_counter <= 0;
 		finished <= 0;
 		err <= 0;
+
+		setup_bits();
 	end
 	2'b10: begin // falling edge
 		finished <= 1;