autogenerate mode tests
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a38631cd17
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@ -1,7 +1,9 @@
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MODES=00 01 10 11
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all:
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for i in 00 01 10 11; do \
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for i in ${MODES}; do \
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make -f run_mode.makefile MODE="$$i"; \
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done
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clean:
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rm -rf obj_dir
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rm -rf obj_dir mode[01][01]*
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#include "Vmode00.h"
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using TopModule = Vmode00;
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#include "write_read.cpp"
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@ -1,34 +0,0 @@
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/* (c) Peter McGoron 2022
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* This Source Code Form is subject to the terms of the Mozilla Public
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* License, v.2.0. If a copy of the MPL was not distributed with this
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* file, You can obtain one at https://mozilla.org/MPL/2.0/.
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*/
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module mode00 (
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input clk,
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input [23:0] data_ctrl,
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input activate,
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input ss,
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input rdy,
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output master_finished
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);
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spi_write_read
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#(
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.POLARITY(0),
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.PHASE(0)
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) base (
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.clk(clk),
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.data_ctrl(data_ctrl),
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.activate(activate),
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.master_finished(master_finished),
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.ss(ss),
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.rdy(rdy)
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);
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initial begin
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$dumpfile("mode00.vcd");
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$dumpvars();
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end
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endmodule
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@ -1,3 +0,0 @@
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#include "Vmode01.h"
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using TopModule = Vmode01;
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#include "write_read.cpp"
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@ -1,34 +0,0 @@
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/* (c) Peter McGoron 2022
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* This Source Code Form is subject to the terms of the Mozilla Public
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* License, v.2.0. If a copy of the MPL was not distributed with this
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* file, You can obtain one at https://mozilla.org/MPL/2.0/.
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*/
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module mode01 (
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input clk,
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input [23:0] data_ctrl,
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input activate,
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input ss,
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input rdy,
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output master_finished
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);
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spi_write_read
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#(
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.POLARITY(0),
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.PHASE(1)
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) base (
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.clk(clk),
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.data_ctrl(data_ctrl),
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.activate(activate),
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.master_finished(master_finished),
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.ss(ss),
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.rdy(rdy)
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);
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initial begin
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$dumpfile("mode01.vcd");
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$dumpvars();
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end
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endmodule
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@ -1,3 +0,0 @@
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#include "Vmode10.h"
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using TopModule = Vmode10;
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#include "write_read.cpp"
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@ -1,3 +0,0 @@
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#include "Vmode11.h"
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using TopModule = Vmode11;
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#include "write_read.cpp"
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@ -1,34 +0,0 @@
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/* (c) Peter McGoron 2022
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* This Source Code Form is subject to the terms of the Mozilla Public
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* License, v.2.0. If a copy of the MPL was not distributed with this
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* file, You can obtain one at https://mozilla.org/MPL/2.0/.
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*/
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module mode11 (
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input clk,
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input [23:0] data_ctrl,
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input activate,
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input ss,
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input rdy,
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output master_finished
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);
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spi_write_read
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#(
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.POLARITY(1),
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.PHASE(1)
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) base (
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.clk(clk),
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.data_ctrl(data_ctrl),
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.activate(activate),
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.master_finished(master_finished),
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.ss(ss),
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.rdy(rdy)
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);
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initial begin
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$dumpfile("mode11.vcd");
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$dumpvars();
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end
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endmodule
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@ -0,0 +1,3 @@
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#include "Vmode@MODE@.h"
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using TopModule = Vmode@MODE@;
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#include "write_read.cpp"
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@ -4,7 +4,7 @@
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* file, You can obtain one at https://mozilla.org/MPL/2.0/.
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*/
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module mode10 (
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module mode@MODE@ (
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input clk,
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input [23:0] data_ctrl,
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input activate,
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spi_write_read
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#(
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.POLARITY(1),
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.PHASE(0)
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.POLARITY(@POLARITY@),
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.PHASE(@PHASE@)
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) base (
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.clk(clk),
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.data_ctrl(data_ctrl),
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);
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initial begin
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$dumpfile("mode10.vcd");
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$dumpfile("mode@MODE@.vcd");
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$dumpvars();
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end
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@ -11,15 +11,14 @@ WAVEFILE=${TESTBENCH_BASE}.vcd
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FILES=${TESTBENCH_BASE}.v ${AUXFILES} ${CPP_TESTBENCH}
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all: obj_dir/V${TESTBENCH_BASE}
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${WAVEFILE}: obj_dir/V${TESTBENCH_BASE}
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./obj_dir/V${TESTBENCH_BASE}
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obj_dir/V${TESTBENCH_BASE}.mk: ${FILES}
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verilator -CFLAGS -Wall -Wno-unused -Wpedantic --trace --cc --exe ${FILES} --top ${TESTBENCH_BASE}
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obj_dir/V${TESTBENCH_BASE}: obj_dir/V${TESTBENCH_BASE}.mk
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make -C obj_dir -f V${TESTBENCH_BASE}.mk
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run:
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./obj_dir/V${TESTBENCH_CASE}
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clean:
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$(RM) obj_dir/*
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${TESTBENCH_BASE}.v: mode_template.v
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sed "s/@PHASE@/`echo ${MODE} | cut -c 2`/g; s/@POLARITY@/`echo ${MODE} | cut -c 1`/g; s/@MODE@/${MODE}/g" mode_template.v > ${TESTBENCH_BASE}.v
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${TESTBENCH_BASE}.cpp: mode_template.cpp
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sed "s/@PHASE@/`echo ${MODE} | cut -c 2`/g; s/@POLARITY@/`echo ${MODE} | cut -c 1`/g; s/@MODE@/${MODE}/g" mode_template.cpp > ${TESTBENCH_BASE}.cpp
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