From 2119ec275bf51fbc393f352618e1aa3d23f4104f Mon Sep 17 00:00:00 2001
From: Peter McGoron <code@mcgoron.com>
Date: Thu, 20 Apr 2023 16:23:23 +0000
Subject: [PATCH] add ready_to_arm to indiciate when the module can accept
 another command

---
 spi_master.v             | 21 +++++++++++++++++++++
 spi_master_ss_template.v |  2 ++
 tests/mk.sh              |  1 +
 tests/simtop.v           |  6 ++++--
 4 files changed, 28 insertions(+), 2 deletions(-)

diff --git a/spi_master.v b/spi_master.v
index 0f07d8a..a69e15b 100644
--- a/spi_master.v
+++ b/spi_master.v
@@ -40,6 +40,7 @@ spi_master
 `endif
 	output reg sck_wire,
 	output reg finished,
+	output reg ready_to_arm,
 	input arm
 );
 
@@ -134,17 +135,28 @@ task cycle_change();
 	end
 endtask
 
+initial ready_to_arm = 1;
+
 always @ (posedge clk) begin
 	case (state)
 	WAIT_ON_ARM: begin
+`ifdef SIMULATION
+		if (!ready_to_arm)
+			$error("not ready to arm in wait_on_arm");
+`endif
 		if (!arm) begin
 			idle_state();
 			finished <= 0;
 		end else begin
 			setup_bits();
+			ready_to_arm <= 0;
 		end
 	end
 	ON_CYCLE: begin
+`ifdef SIMULATION
+		if (ready_to_arm)
+			$error("ready_to_arm while on cycle");
+`endif
 		if (sck) begin // rising edge
 			if (PHASE == 1) begin
 				write_data();
@@ -174,6 +186,10 @@ always @ (posedge clk) begin
 		end
 	end
 	CYCLE_WAIT: begin
+`ifdef SIMULATION
+		if (ready_to_arm)
+			$error("ready_to_arm while in cycle wait");
+`endif
 		if (timer == CYCLE_HALF_WAIT) begin
 			timer <= 1;
 			cycle_change();
@@ -182,10 +198,15 @@ always @ (posedge clk) begin
 		end
 	end
 	WAIT_FINISHED: begin
+`ifdef SIMULATION
+		if (ready_to_arm)
+			$error("ready_to_arm while in wait finished");
+`endif
 		finished <= 1;
 		idle_state();
 		if (!arm) begin
 			state <= WAIT_ON_ARM;
+			ready_to_arm <= 1;
 		end
 	end
 	endcase
diff --git a/spi_master_ss_template.v b/spi_master_ss_template.v
index e2e0cc4..f231f70 100644
--- a/spi_master_ss_template.v
+++ b/spi_master_ss_template.v
@@ -27,6 +27,7 @@ module `SPI_MASTER_SS_NAME
 `endif
 	output sck_wire,
 	output finished,
+	output ready_to_arm,
 	output ss_L,
 	input arm
 );
@@ -54,6 +55,7 @@ assign ss_L = !ss;
 `endif
 	.sck_wire(sck_wire),
 	.finished(finished),
+	.ready_to_arm(ready_to_arm),
 	.arm(arm_master)
 );
 
diff --git a/tests/mk.sh b/tests/mk.sh
index 417bd3a..707b753 100755
--- a/tests/mk.sh
+++ b/tests/mk.sh
@@ -19,6 +19,7 @@ run_test() {
 		-GWID_LEN=$WIDLEN \
 		-DSPI_MASTER_TYPE=$MASTER_TYPE -DSPI_SLAVE_TYPE=$SLAVE_TYPE \
 		-DVCDFILE="\"$DIR.fst\"" \
+		-DSIMULATION \
 		--Mdir $DIR \
 		$EXTARG \
 		simtop.v write_read.cpp $MODS \
diff --git a/tests/simtop.v b/tests/simtop.v
index a1461bc..71981a8 100644
--- a/tests/simtop.v
+++ b/tests/simtop.v
@@ -26,6 +26,7 @@ module simtop
 `endif
 	input rdy,
 	output master_finished,
+	output ready_to_arm,
 	output err
 );
 
@@ -74,6 +75,7 @@ reg slave_error;
 `endif
 	.sck_wire(sck),
 	.finished(master_finished),
+	.ready_to_arm(ready_to_arm),
 	.arm(activate)
 );
 
@@ -99,11 +101,11 @@ reg slave_error;
 	.err(err)
 );
 
-/*
+`ifdef SIMULATION
 initial begin
 	$dumpfile(`VCDFILE);
 	$dumpvars;
 end
-*/
+`endif
 
 endmodule