start cleanup of SPI
This commit is contained in:
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df6fe45d65
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75
spi_master.v
75
spi_master.v
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@ -1,4 +1,4 @@
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/* (c) Peter McGoron 2022 v0.3
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/* (c) Peter McGoron 2022 v0.4
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* This Source Code Form is subject to the terms of the Mozilla Public
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* License, v.2.0. If a copy of the MPL was not distributed with this
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* file, You can obtain one at https://mozilla.org/MPL/2.0/.
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@ -9,17 +9,9 @@
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* the input).
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*/
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module
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`ifdef SPI_MASTER_NO_READ
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spi_master_no_read
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`else
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`ifdef SPI_MASTER_NO_WRITE
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spi_master_no_write
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`else
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spi_master
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`endif
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`endif
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#(
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module spi_master #(
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parameter ENABLE_MISO = 1, // Enable MISO and from_slave port
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parameter ENABLE_MOSI = 1, // Enable MOSI and to_slave port
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parameter WID = 24, // Width of bits per transaction.
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parameter WID_LEN = 5, // Length in bits required to store WID
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parameter CYCLE_HALF_WAIT = 1, // Half of the wait time of a cycle minus 1.
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@ -27,25 +19,22 @@ spi_master
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parameter TIMER_LEN = 3, // Length in bits required to store CYCLE_HALF_WAIT
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parameter POLARITY = 0, // 0 = sck idle low, 1 = sck idle high
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parameter PHASE = 0 // 0 = rising-read falling-write, 1 = rising-write falling-read.
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)
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(
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) (
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input clk,
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input rst_L,
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`ifndef SPI_MASTER_NO_READ
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output reg [WID-1:0] from_slave,
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input miso,
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`endif
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`ifndef SPI_MASTER_NO_WRITE
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input [WID-1:0] to_slave,
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output reg mosi,
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`endif
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output reg sck_wire,
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output reg finished,
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output reg ready_to_arm,
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input arm
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);
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`ifndef SPI_MASTER_NO_READ
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/* MISO is almost always an external wire, so buffer it.
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* This might not be necessary, since the master and slave do not respond
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* immediately to changes in the wires, but this is just to be safe.
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@ -56,11 +45,10 @@ spi_master
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reg miso_hot = 0;
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reg read_miso = 0;
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always @ (posedge clk) begin
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always @ (posedge clk) if (ENABLE_MISO) begin
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read_miso <= miso_hot;
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miso_hot <= miso;
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end
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`endif
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parameter WAIT_ON_ARM = 0;
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parameter ON_CYCLE = 1;
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@ -71,9 +59,7 @@ reg [1:0] state = WAIT_ON_ARM;
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reg [WID_LEN-1:0] bit_counter = 0;
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reg [TIMER_LEN-1:0] timer = 0;
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`ifndef SPI_MASTER_NO_WRITE
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reg [WID-1:0] send_buf = 0;
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`endif
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reg sck = 0;
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assign sck_wire = sck;
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@ -84,25 +70,23 @@ task idle_state();
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end else begin
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sck <= 1;
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end
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`ifndef SPI_MASTER_NO_WRITE
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mosi <= 0;
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`endif
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if (ENABLE_MOSI) mosi <= 0;
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timer <= 0;
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bit_counter <= 0;
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endtask
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task read_data();
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`ifndef SPI_MASTER_NO_READ
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from_slave <= from_slave << 1;
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from_slave[0] <= read_miso;
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`endif
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if (ENABLE_MISO) begin
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from_slave <= from_slave << 1;
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from_slave[0] <= read_miso;
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end
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endtask
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task write_data();
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`ifndef SPI_MASTER_NO_WRITE
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mosi <= send_buf[WID-1];
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send_buf <= send_buf << 1;
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`endif
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if (ENABLE_MOSI) begin
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mosi <= send_buf[WID-1];
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send_buf <= send_buf << 1;
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end
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endtask
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task setup_bits();
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@ -113,15 +97,15 @@ task setup_bits();
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* For mode 01 and mode 10, the first action is a WRITE.
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*/
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if (POLARITY == PHASE) begin
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`ifndef SPI_MASTER_NO_WRITE
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mosi <= to_slave[WID-1];
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send_buf <= to_slave << 1;
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`endif
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if (ENABLE_MOSI) begin
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mosi <= to_slave[WID-1];
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send_buf <= to_slave << 1;
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end
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state <= CYCLE_WAIT;
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end else begin
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`ifndef SPI_MASTER_NO_WRITE
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send_buf <= to_slave;
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`endif
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if (ENABLE_MISO) begin
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send_buf <= to_slave;
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end
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state <= ON_CYCLE;
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end
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endtask
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@ -144,12 +128,8 @@ always @ (posedge clk) begin
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finished <= 0;
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state <= WAIT_ON_ARM;
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ready_to_arm <= 1;
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`ifndef SPI_MASTER_NO_READ
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from_slave <= 0;
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`endif
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`ifndef SPI_MASTER_NO_WRITE
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send_buf <= 0;
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`endif
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if (ENABLE_MISO) from_slave <= 0;
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if (ENABLE_MOSI) send_buf <= 0;
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end else case (state)
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WAIT_ON_ARM: begin
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`ifdef SIMULATION
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@ -225,4 +205,3 @@ always @ (posedge clk) begin
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end
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endmodule
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`undefineall
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@ -1,3 +0,0 @@
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`define SPI_MASTER_NO_READ
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/* verilator lint_off DECLFILENAME */
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`include "spi_master.v"
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@ -1,3 +0,0 @@
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`define SPI_MASTER_NO_WRITE
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/* verilator lint_off DECLFILENAME */
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`include "spi_master.v"
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@ -1,4 +0,0 @@
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`define SPI_MASTER_SS_NAME spi_master_ss
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`define SPI_MASTER_NAME spi_master
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/* verilator lint_off DECLFILENAME */
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`include "spi_master_ss_template.v"
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@ -1,5 +0,0 @@
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`define SPI_MASTER_SS_NAME spi_master_ss_no_read
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`define SPI_MASTER_NAME spi_master_no_read
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`define SPI_MASTER_NO_READ
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/* verilator lint_off DECLFILENAME */
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`include "spi_master_ss_template.v"
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@ -1,5 +0,0 @@
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`define SPI_MASTER_SS_NAME spi_master_ss_no_write
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`define SPI_MASTER_NAME spi_master_no_write
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`define SPI_MASTER_NO_WRITE
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/* verilator lint_off DECLFILENAME */
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`include "spi_master_ss_template.v"
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@ -1,36 +1,39 @@
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/* (c) Peter McGoron 2022 v0.3
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/* (c) Peter McGoron 2022 v0.4
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* This Source Code Form is subject to the terms of the Mozilla Public
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* License, v.2.0. If a copy of the MPL was not distributed with this
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* file, You can obtain one at https://mozilla.org/MPL/2.0/.
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*/
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/* spi master with integrated ability to wait a certain amount of cycles
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* after activating SS.
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*/
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module `SPI_MASTER_SS_NAME
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module spi_master_ss
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#(
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parameter SS_WAIT = 1, /* Amount of cycles to wait for SS
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to enable */
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parameter SS_WAIT_TIMER_LEN = 2, /* Amount of bits required to
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store the SS wait time */
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parameter ENABLE_MISO = 1,
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parameter ENABLE_MOSI = 1,
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parameter WID = 24,
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parameter WID_LEN = 5,
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parameter CYCLE_HALF_WAIT = 1,
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parameter TIMER_LEN = 3,
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parameter SS_WAIT = 1,
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parameter SS_WAIT_TIMER_LEN = 2,
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parameter POLARITY = 0,
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parameter PHASE = 0
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)
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(
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) (
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input clk,
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input rst_L,
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`ifndef SPI_MASTER_NO_READ
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output [WID-1:0] from_slave,
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input miso,
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`endif
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`ifndef SPI_MASTER_NO_WRITE
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input [WID-1:0] to_slave,
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output reg mosi,
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`endif
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output sck_wire,
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output finished,
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output ready_to_arm,
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@ -42,7 +45,9 @@ reg ss = 0;
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reg arm_master = 0;
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assign ss_L = !ss;
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`SPI_MASTER_NAME #(
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spi_master #(
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.ENABLE_MISO(ENABLE_MISO),
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.ENABLE_MOSI(ENABLE_MOSI),
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.WID(WID),
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.WID_LEN(WID_LEN),
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.CYCLE_HALF_WAIT(CYCLE_HALF_WAIT),
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@ -52,14 +57,13 @@ assign ss_L = !ss;
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) master (
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.clk(clk),
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.rst_L(rst_L),
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`ifndef SPI_MASTER_NO_READ
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.from_slave(from_slave),
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.miso(miso),
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`endif
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`ifndef SPI_MASTER_NO_WRITE
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.to_slave(to_slave),
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.mosi(mosi),
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`endif
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.sck_wire(sck_wire),
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.finished(finished),
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.ready_to_arm(ready_to_arm),
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@ -120,4 +124,3 @@ always @ (posedge clk) begin
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end
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endmodule
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`undefineall
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86
spi_slave.v
86
spi_slave.v
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@ -1,51 +1,41 @@
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/* (c) Peter McGoron 2022 v0.3
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/* (c) Peter McGoron 2022 v0.4
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* This Source Code Form is subject to the terms of the Mozilla Public
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* License, v.2.0. If a copy of the MPL was not distributed with this
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* file, You can obtain one at https://mozilla.org/MPL/2.0/.
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*/
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module
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`ifdef SPI_SLAVE_NO_READ
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spi_slave_no_read
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`elsif SPI_SLAVE_NO_WRITE
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spi_slave_no_write
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`else
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spi_slave
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`endif
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#(
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module spi_slave #(
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parameter ENABLE_MISO = 1, // Enable MISO and to_master port
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parameter ENABLE_MOSI = 1, // Enable MOSI and from_master port
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parameter WID = 24, // Width of bits per transaction.
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parameter WID_LEN = 5, // Length in bits required to store WID
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parameter POLARITY = 0,
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parameter PHASE = 0 // 0 = rising-read falling-write, 1 = rising-write falling-read.
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)
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(
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) (
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input clk,
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input rst_L,
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input sck,
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input ss_L,
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`ifndef SPI_SLAVE_NO_READ
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output reg [WID-1:0] from_master,
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input mosi,
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`endif
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`ifndef SPI_SLAVE_NO_WRITE
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input [WID-1:0] to_master,
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output reg miso,
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`endif
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output reg finished,
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input rdy,
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output reg err
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);
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`ifndef SPI_SLAVE_NO_READ
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/* MOSI is almost always an external wire, so buffer it. */
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reg mosi_hot = 0;
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reg read_mosi = 0;
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always @ (posedge clk) begin
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always @ (posedge clk) if (ENABLE_MOSI) begin
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read_mosi <= mosi_hot;
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mosi_hot <= mosi;
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end
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`endif
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wire ss = !ss_L;
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reg sck_delay = 0;
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@ -58,34 +48,34 @@ reg [WID-1:0] send_buf = 0;
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`endif
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task read_data();
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`ifndef SPI_SLAVE_NO_READ
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from_master <= from_master << 1;
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from_master[0] <= read_mosi;
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`endif
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if (ENABLE_MOSI) begin
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from_master <= from_master << 1;
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from_master[0] <= read_mosi;
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end
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endtask
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task write_data();
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`ifndef SPI_SLAVE_NO_WRITE
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send_buf <= send_buf << 1;
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miso <= send_buf[WID-1];
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`endif
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if (ENABLE_MISO) begin
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send_buf <= send_buf << 1;
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miso <= send_buf[WID-1];
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end
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endtask
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task setup_bits();
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`ifndef SPI_SLAVE_NO_WRITE
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/* at Mode 00, the transmission starts with
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* a rising edge, and at mode 11, it starts with a falling
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* edge. For both modes, these are READs.
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*
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* For mode 01 and mode 10, the first action is a WRITE.
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*/
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if (POLARITY == PHASE) begin
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miso <= to_master[WID-1];
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send_buf <= to_master << 1;
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end else begin
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send_buf <= to_master;
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if (ENABLE_MISO) begin
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/* at Mode 00, the transmission starts with
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* a rising edge, and at mode 11, it starts with a falling
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* edge. For both modes, these are READs.
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*
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* For mode 01 and mode 10, the first action is a WRITE.
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*/
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if (POLARITY == PHASE) begin
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miso <= to_master[WID-1];
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send_buf <= to_master << 1;
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end else begin
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send_buf <= to_master;
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end
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end
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`endif
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endtask
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task check_counter();
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@ -102,13 +92,14 @@ always @ (posedge clk) begin
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bit_counter <= 0;
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ss_delay <= 0;
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ready_at_start <= 0;
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`ifndef SPI_SLAVE_NO_READ
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from_master <= 0;
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`endif
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`ifndef SPI_SLAVE_NO_WRITE
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miso <= 0;
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send_buf <= 0;
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`endif
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if (ENABLE_MOSI) from_master <= 0;
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if (ENABLE_MISO) begin
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miso <= 0;
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send_buf <= 0;
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end
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finished <= 0;
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err <= 0;
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end else begin
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@ -163,4 +154,3 @@ always @ (posedge clk) begin
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end
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endmodule
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`undefineall
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@ -1,3 +0,0 @@
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`define SPI_SLAVE_NO_READ
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/* verilator lint_off DECLFILENAME */
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`include "spi_slave.v"
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@ -1,3 +0,0 @@
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`define SPI_SLAVE_NO_WRITE
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/* verilator lint_off DECLFILENAME */
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`include "spi_slave.v"
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