add metastability workaround
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039507d13a
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19
spi_master.v
19
spi_master.v
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@ -4,6 +4,11 @@
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* file, You can obtain one at https://mozilla.org/MPL/2.0/.
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* file, You can obtain one at https://mozilla.org/MPL/2.0/.
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*/
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*/
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/* CYCLE_HALF_WAIT should take into account the setup time of the slave
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* device, and also master buffering (MISO is one cycle off to stabilize
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* the input).
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*/
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module
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module
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`ifdef SPI_MASTER_NO_READ
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`ifdef SPI_MASTER_NO_READ
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spi_master_no_read
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spi_master_no_read
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@ -14,7 +19,6 @@ spi_master_no_write
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spi_master
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spi_master
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`endif
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`endif
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`endif
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`endif
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#(
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#(
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parameter WID = 24, // Width of bits per transaction.
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parameter WID = 24, // Width of bits per transaction.
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parameter WID_LEN = 5, // Length in bits required to store WID
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parameter WID_LEN = 5, // Length in bits required to store WID
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@ -39,6 +43,17 @@ spi_master
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input arm
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input arm
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);
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);
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`ifndef SPI_MASTER_NO_READ
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/* MISO is almost always an external wire, so buffer it. */
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reg miso_hot = 0;
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reg read_miso = 0;
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always @ (posedge clk) begin
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read_miso <= miso_hot;
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miso_hot <= miso;
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end
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`endif
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parameter WAIT_ON_ARM = 0;
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parameter WAIT_ON_ARM = 0;
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parameter ON_CYCLE = 1;
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parameter ON_CYCLE = 1;
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parameter CYCLE_WAIT = 2;
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parameter CYCLE_WAIT = 2;
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@ -71,7 +86,7 @@ endtask
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task read_data();
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task read_data();
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`ifndef SPI_MASTER_NO_READ
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`ifndef SPI_MASTER_NO_READ
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from_slave <= from_slave << 1;
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from_slave <= from_slave << 1;
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from_slave[0] <= miso;
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from_slave[0] <= read_miso;
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`endif
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`endif
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endtask
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endtask
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15
spi_slave.v
15
spi_slave.v
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@ -24,7 +24,7 @@ spi_slave
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input ss_L,
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input ss_L,
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`ifndef SPI_SLAVE_NO_READ
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`ifndef SPI_SLAVE_NO_READ
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output reg [WID-1:0] from_master,
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output reg [WID-1:0] from_master,
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input reg mosi,
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input mosi,
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`endif
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`endif
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`ifndef SPI_SLAVE_NO_WRITE
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`ifndef SPI_SLAVE_NO_WRITE
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input [WID-1:0] to_master,
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input [WID-1:0] to_master,
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@ -35,6 +35,17 @@ spi_slave
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output reg err
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output reg err
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);
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);
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`ifndef SPI_SLAVE_NO_READ
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/* MOSI is almost always an external wire, so buffer it. */
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reg mosi_hot = 0;
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reg read_mosi = 0;
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always @ (posedge clk) begin
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read_mosi <= mosi_hot;
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mosi_hot <= mosi;
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end
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`endif
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wire ss = !ss_L;
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wire ss = !ss_L;
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reg sck_delay = 0;
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reg sck_delay = 0;
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reg [WID_LEN-1:0] bit_counter = 0;
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reg [WID_LEN-1:0] bit_counter = 0;
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@ -48,7 +59,7 @@ reg [WID-1:0] send_buf = 0;
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task read_data();
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task read_data();
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`ifndef SPI_SLAVE_NO_READ
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`ifndef SPI_SLAVE_NO_READ
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from_master <= from_master << 1;
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from_master <= from_master << 1;
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from_master[0] <= mosi;
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from_master[0] <= read_mosi;
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`endif
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`endif
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endtask
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endtask
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