diff --git a/spi_master.v b/spi_master.v
index f3e67a1..5610119 100644
--- a/spi_master.v
+++ b/spi_master.v
@@ -2,7 +2,7 @@ module spi_master
 #(
 	parameter WID = 24, // Width of bits per transaction.
 	parameter WID_LEN = 5, // Length in bits required to store WID
-	parameter CYCLE_HALF_WAIT = 3, // Half of the wait time of a cycle
+	parameter CYCLE_HALF_WAIT = 1, // Half of the wait time of a cycle
 	parameter TIMER_LEN = 3, // Length in bits required to store CYCLE_HALF_WAIT
 	parameter POLARITY = 0, // 0 = sck idle low, 1 = sck idle high
 	parameter PHASE = 0 // 0 = rising-read falling-write, 1 = rising-write falling-read.
diff --git a/spi_slave.v b/spi_slave.v
index 8efce47..54a5051 100644
--- a/spi_slave.v
+++ b/spi_slave.v
@@ -18,6 +18,7 @@ module spi_slave
 	output miso,
 `endif
 	output finished,
+	input rdy,
 	output err
 );
 
@@ -25,6 +26,7 @@ wire ss = !ss_L;
 reg sck_delay = 0;
 reg [WID_LEN-1:0] bit_counter = 0;
 reg ss_delay = 0;
+reg ready_at_start = 0;
 
 `ifndef SPI_SLAVE_NO_WRITE
 reg [WID-1:0] send_buf = 0;
@@ -59,6 +61,14 @@ task setup_bits();
 	end
 endtask
 
+task check_counter();
+	if (bit_counter == WID) begin
+		err <= ready_at_start;
+	end else begin
+		bit_counter <= bit_counter + 1;
+	end
+endtask
+
 always @ (posedge clk) begin
 	sck_delay <= sck;
 	ss_delay <= ss;
@@ -68,11 +78,12 @@ always @ (posedge clk) begin
 		bit_counter <= 0;
 		finished <= 0;
 		err <= 0;
+		ready_at_start <= rdy;
 
 		setup_bits();
 	end
 	2'b10: begin // falling edge
-		finished <= 1;
+		finished <= ready_at_start;
 	end
 	2'b11: begin
 		case ({sck_delay, sck})
@@ -84,11 +95,7 @@ always @ (posedge clk) begin
 			end
 
 			if (POLARITY == 0) begin
-				if (bit_counter == WID) begin
-					err <= 1;
-				end else begin
-					bit_counter <= bit_counter + 1;
-				end
+				check_counter();
 			end
 		end
 		2'b10: begin // falling edge
@@ -99,17 +106,16 @@ always @ (posedge clk) begin
 			end
 
 			if (POLARITY == 1) begin
-				if (bit_counter == WID) begin
-					err <= 1;
-				end else begin
-					bit_counter <= bit_counter + 1;
-				end
+				check_counter();
 			end
 		end
 		default: ;
 		endcase
 	end
-	2'b00: ;
+	2'b00: if (!rdy) begin
+		finished <= 0;
+		err <= 0;
+	end
 	endcase
 end
 
diff --git a/test_spi_write_read_mode0.cpp b/test_spi_write_read_mode0.cpp
index bbbf03c..631761e 100644
--- a/test_spi_write_read_mode0.cpp
+++ b/test_spi_write_read_mode0.cpp
@@ -25,9 +25,11 @@ int main(int argc, char **argv) {
 	sim->ss = 0;
 	sim->clk = 0;
 	sim->activate = 0;
+	sim->rdy = 0;
 
 	progress_n(8);
 	sim->ss = 1;
+	sim->rdy = 1;
 	progress();
 
 	sim->data_ctrl = 0b110011011111001100011111;
@@ -36,7 +38,21 @@ int main(int argc, char **argv) {
 	while (!sim->master_finished)
 		progress();
 	progress_n(5);
+	sim->activate = 0;
 	sim->ss = 0;
+	sim->rdy = 0;
+	progress_n(5);
+
+	sim->data_ctrl = 0xFE3456;
+	sim->activate = 1;
+	sim->ss = 1;
+	sim->rdy = 1;
+	while (!sim->master_finished)
+		progress();
+	progress_n(5);
+	sim->activate = 0;
+	sim->ss = 0;
+	sim->rdy = 0;
 	progress_n(5);
 
 	sim->final();
diff --git a/test_spi_write_read_mode0.v b/test_spi_write_read_mode0.v
index 56be197..554b92e 100644
--- a/test_spi_write_read_mode0.v
+++ b/test_spi_write_read_mode0.v
@@ -4,6 +4,7 @@ module test_spi_write_read_mode0
 	input [23:0] data_ctrl,
 	input activate,
 	input ss,
+	input rdy,
 	output master_finished,
 	output slave_finished,
 	output slave_error
@@ -31,7 +32,7 @@ spi_master master
 reg [23:0] data_from_master;
 reg [23:0] data_to_master = 24'b111011011100010101010101;
 
-spi_slave spi_slave
+spi_slave slave
 (
 	.clk(clk),
 	.sck(sck),
@@ -41,6 +42,7 @@ spi_slave spi_slave
 	.mosi(mosi),
 	.miso(miso),
 	.finished(slave_finished),
+	.rdy(rdy),
 	.err(slave_error)
 );