peter
/
spi
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

mode 00, write from master to slave works

This commit is contained in:
Peter McGoron 2022-07-21 01:09:45 -04:00
parent 6f000b64ec
commit c4f401cff2
3 changed files with 35 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Makefile
View File

@ -9,7 +9,7 @@ all: obj_dir/V${TESTBENCH_BASE}
./obj_dir/V${TESTBENCH_BASE} && gtkwave ${WAVEFILE} ./obj_dir/V${TESTBENCH_BASE} && gtkwave ${WAVEFILE}
obj_dir/V${TESTBENCH_BASE}.mk: ${FILES} obj_dir/V${TESTBENCH_BASE}.mk: ${FILES}
verilator --trace --cc --exe ${FILES} --top ${TESTBENCH_BASE} verilator -Wall -Wno-unused -Wpedantic --trace --cc --exe ${FILES} --top ${TESTBENCH_BASE}
obj_dir/V${TESTBENCH_BASE}: obj_dir/V${TESTBENCH_BASE}.mk obj_dir/V${TESTBENCH_BASE}: obj_dir/V${TESTBENCH_BASE}.mk
make -C obj_dir -f V${TESTBENCH_BASE}.mk make -C obj_dir -f V${TESTBENCH_BASE}.mk

24
spi_master.v
View File

@ -72,8 +72,22 @@ always @ (posedge clk) begin
idle_state(); idle_state();
finished <= 0; finished <= 0;
end else begin end else begin
state <= ON_CYCLE; /* at Mode 00, the transmission starts with
* a rising edge, and at mode 11, it starts
* with a falling edge. For both modes,
* these are READs.
*
* For mode 01 and mode 10, the first
* action is a WRITE.
*/
if (POLARITY == PHASE) begin
mosi <= to_slave[WID-1];
send_buf <= to_slave << 1;
state <= CYCLE_WAIT;
end else begin
send_buf <= to_slave; send_buf <= to_slave;
state <= ON_CYCLE;
end
end end
end end
ON_CYCLE: begin ON_CYCLE: begin
@ -84,7 +98,7 @@ always @ (posedge clk) begin
read_data(); read_data();
end end
if (POLARITY == 1) begin if (POLARITY == 0) begin
bit_counter <= bit_counter + 1; bit_counter <= bit_counter + 1;
end end
end else begin // falling edge end else begin // falling edge
@ -94,7 +108,7 @@ always @ (posedge clk) begin
write_data(); write_data();
end end
if (POLARITY == 0) begin if (POLARITY == 1) begin
bit_counter <= bit_counter + 1; bit_counter <= bit_counter + 1;
end end
end end
@ -103,7 +117,9 @@ always @ (posedge clk) begin
CYCLE_WAIT: begin CYCLE_WAIT: begin
if (timer == CYCLE_HALF_WAIT) begin if (timer == CYCLE_HALF_WAIT) begin
timer <= 0; timer <= 0;
if (bit_counter == WID) begin // Stop transfer when the clock returns
// to its original polarity.
if (bit_counter == WID && sck == POLARITY) begin
state <= WAIT_FINISHED; state <= WAIT_FINISHED;
end else begin end else begin
state <= ON_CYCLE; state <= ON_CYCLE;

16
spi_slave.v
View File

@ -55,11 +55,7 @@ always @ (posedge clk) begin
err <= 0; err <= 0;
end end
2'b10: begin // falling edge 2'b10: begin // falling edge
if (bit_counter == WID) begin
finished <= 1; finished <= 1;
end else begin
err <= 1;
end
end end
2'b11: begin 2'b11: begin
case ({sck_delay, sck}) case ({sck_delay, sck})
@ -70,10 +66,14 @@ always @ (posedge clk) begin
read_data(); read_data();
end end
if (POLARITY == 1) begin if (POLARITY == 0) begin
if (bit_counter == WID) begin
err <= 1;
end else begin
bit_counter <= bit_counter + 1; bit_counter <= bit_counter + 1;
end end
end end
end
2'b10: begin // falling edge 2'b10: begin // falling edge
if (PHASE == 1) begin if (PHASE == 1) begin
read_data(); read_data();
@ -81,10 +81,14 @@ always @ (posedge clk) begin
write_data(); write_data();
end end
if (POLARITY == 0) begin if (POLARITY == 1) begin
if (bit_counter == WID) begin
err <= 1;
end else begin
bit_counter <= bit_counter + 1; bit_counter <= bit_counter + 1;
end end
end end
end
default: ; default: ;
endcase endcase
end end