mode 00, write from master to slave works
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parent
6f000b64ec
commit
c4f401cff2
2
Makefile
2
Makefile
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@ -9,7 +9,7 @@ all: obj_dir/V${TESTBENCH_BASE}
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./obj_dir/V${TESTBENCH_BASE} && gtkwave ${WAVEFILE}
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./obj_dir/V${TESTBENCH_BASE} && gtkwave ${WAVEFILE}
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obj_dir/V${TESTBENCH_BASE}.mk: ${FILES}
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obj_dir/V${TESTBENCH_BASE}.mk: ${FILES}
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verilator --trace --cc --exe ${FILES} --top ${TESTBENCH_BASE}
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verilator -Wall -Wno-unused -Wpedantic --trace --cc --exe ${FILES} --top ${TESTBENCH_BASE}
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obj_dir/V${TESTBENCH_BASE}: obj_dir/V${TESTBENCH_BASE}.mk
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obj_dir/V${TESTBENCH_BASE}: obj_dir/V${TESTBENCH_BASE}.mk
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make -C obj_dir -f V${TESTBENCH_BASE}.mk
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make -C obj_dir -f V${TESTBENCH_BASE}.mk
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26
spi_master.v
26
spi_master.v
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@ -72,8 +72,22 @@ always @ (posedge clk) begin
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idle_state();
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idle_state();
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finished <= 0;
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finished <= 0;
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end else begin
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end else begin
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state <= ON_CYCLE;
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/* at Mode 00, the transmission starts with
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send_buf <= to_slave;
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* a rising edge, and at mode 11, it starts
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* with a falling edge. For both modes,
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* these are READs.
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*
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* For mode 01 and mode 10, the first
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* action is a WRITE.
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*/
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if (POLARITY == PHASE) begin
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mosi <= to_slave[WID-1];
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send_buf <= to_slave << 1;
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state <= CYCLE_WAIT;
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end else begin
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send_buf <= to_slave;
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state <= ON_CYCLE;
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end
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end
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end
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end
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end
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ON_CYCLE: begin
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ON_CYCLE: begin
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@ -84,7 +98,7 @@ always @ (posedge clk) begin
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read_data();
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read_data();
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end
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end
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if (POLARITY == 1) begin
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if (POLARITY == 0) begin
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bit_counter <= bit_counter + 1;
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bit_counter <= bit_counter + 1;
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end
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end
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end else begin // falling edge
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end else begin // falling edge
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@ -94,7 +108,7 @@ always @ (posedge clk) begin
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write_data();
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write_data();
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end
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end
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if (POLARITY == 0) begin
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if (POLARITY == 1) begin
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bit_counter <= bit_counter + 1;
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bit_counter <= bit_counter + 1;
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end
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end
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end
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end
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@ -103,7 +117,9 @@ always @ (posedge clk) begin
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CYCLE_WAIT: begin
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CYCLE_WAIT: begin
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if (timer == CYCLE_HALF_WAIT) begin
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if (timer == CYCLE_HALF_WAIT) begin
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timer <= 0;
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timer <= 0;
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if (bit_counter == WID) begin
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// Stop transfer when the clock returns
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// to its original polarity.
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if (bit_counter == WID && sck == POLARITY) begin
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state <= WAIT_FINISHED;
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state <= WAIT_FINISHED;
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end else begin
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end else begin
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state <= ON_CYCLE;
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state <= ON_CYCLE;
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22
spi_slave.v
22
spi_slave.v
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@ -55,11 +55,7 @@ always @ (posedge clk) begin
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err <= 0;
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err <= 0;
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end
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end
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2'b10: begin // falling edge
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2'b10: begin // falling edge
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if (bit_counter == WID) begin
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finished <= 1;
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finished <= 1;
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end else begin
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err <= 1;
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end
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end
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end
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2'b11: begin
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2'b11: begin
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case ({sck_delay, sck})
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case ({sck_delay, sck})
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@ -70,8 +66,12 @@ always @ (posedge clk) begin
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read_data();
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read_data();
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end
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end
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if (POLARITY == 1) begin
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if (POLARITY == 0) begin
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bit_counter <= bit_counter + 1;
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if (bit_counter == WID) begin
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err <= 1;
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end else begin
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bit_counter <= bit_counter + 1;
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end
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end
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end
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end
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end
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2'b10: begin // falling edge
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2'b10: begin // falling edge
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@ -81,8 +81,12 @@ always @ (posedge clk) begin
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write_data();
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write_data();
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end
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end
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if (POLARITY == 0) begin
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if (POLARITY == 1) begin
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bit_counter <= bit_counter + 1;
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if (bit_counter == WID) begin
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err <= 1;
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end else begin
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bit_counter <= bit_counter + 1;
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end
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end
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end
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end
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end
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default: ;
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default: ;
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