From d8b011110ad743771183ca7489401c11fe801e4f Mon Sep 17 00:00:00 2001 From: Peter McGoron Date: Thu, 21 Jul 2022 03:01:58 -0400 Subject: [PATCH] successfully test mode01, add Makefile --- tests/Makefile | 7 +++++++ tests/mode01.cpp | 3 +++ tests/mode01.v | 34 ++++++++++++++++++++++++++++++++++ tests/run.sh | 5 ----- tests/run_mode.makefile | 2 +- tests/spi_write_read.v | 13 +++++++++---- 6 files changed, 54 insertions(+), 10 deletions(-) create mode 100644 tests/Makefile create mode 100644 tests/mode01.cpp create mode 100644 tests/mode01.v delete mode 100755 tests/run.sh diff --git a/tests/Makefile b/tests/Makefile new file mode 100644 index 0000000..db36b8c --- /dev/null +++ b/tests/Makefile @@ -0,0 +1,7 @@ +all: + for i in 00 01; do \ + make -f run_mode.makefile MODE="$$i"; \ + done + +clean: + rm -rf obj_dir diff --git a/tests/mode01.cpp b/tests/mode01.cpp new file mode 100644 index 0000000..4b5ea78 --- /dev/null +++ b/tests/mode01.cpp @@ -0,0 +1,3 @@ +#include "Vmode01.h" +using TopModule = Vmode01; +#include "write_read.cpp" diff --git a/tests/mode01.v b/tests/mode01.v new file mode 100644 index 0000000..4fb9e52 --- /dev/null +++ b/tests/mode01.v @@ -0,0 +1,34 @@ +/* (c) Peter McGoron 2022 + * This Source Code Form is subject to the terms of the Mozilla Public + * License, v.2.0. If a copy of the MPL was not distributed with this + * file, You can obtain one at https://mozilla.org/MPL/2.0/. + */ + +module mode01 ( + input clk, + input [23:0] data_ctrl, + input activate, + input ss, + input rdy, + output master_finished +); + +spi_write_read +#( + .POLARITY(0), + .PHASE(1) +) base ( + .clk(clk), + .data_ctrl(data_ctrl), + .activate(activate), + .master_finished(master_finished), + .ss(ss), + .rdy(rdy) +); + +initial begin + $dumpfile("mode01.vcd"); + $dumpvars(); +end + +endmodule diff --git a/tests/run.sh b/tests/run.sh deleted file mode 100755 index ea99836..0000000 --- a/tests/run.sh +++ /dev/null @@ -1,5 +0,0 @@ -#!/bin/sh - -for i in 00; do - make -f run_mode.makefile MODE="$i" -done diff --git a/tests/run_mode.makefile b/tests/run_mode.makefile index 31b6644..b03da8e 100644 --- a/tests/run_mode.makefile +++ b/tests/run_mode.makefile @@ -12,7 +12,7 @@ WAVEFILE=${TESTBENCH_BASE}.vcd FILES=${TESTBENCH_BASE}.v ${AUXFILES} ${CPP_TESTBENCH} all: obj_dir/V${TESTBENCH_BASE} - ./obj_dir/V${TESTBENCH_BASE} && gtkwave ${WAVEFILE} + ./obj_dir/V${TESTBENCH_BASE} obj_dir/V${TESTBENCH_BASE}.mk: ${FILES} verilator -CFLAGS -Wall -Wno-unused -Wpedantic --trace --cc --exe ${FILES} --top ${TESTBENCH_BASE} diff --git a/tests/spi_write_read.v b/tests/spi_write_read.v index 8045a1c..efd9e88 100644 --- a/tests/spi_write_read.v +++ b/tests/spi_write_read.v @@ -27,8 +27,11 @@ reg [23:0] from_slave_data; reg slave_finished; reg slave_error; -spi_master master -( +spi_master +#( + .POLARITY(POLARITY), + .PHASE(PHASE) +) master ( .clk(clk), .to_slave(data_ctrl), .from_slave(from_slave_data), @@ -42,8 +45,10 @@ spi_master master reg [23:0] data_from_master; reg [23:0] data_to_master = 24'b111011011100010101010101; -spi_slave slave -( +spi_slave #( + .POLARITY(POLARITY), + .PHASE(PHASE) +) slave ( .clk(clk), .sck(sck), .ss_L(ss_L),