/* (c) Peter McGoron 2022-2024 v0.4
 *
 * This code is disjunctively dual-licensed under the MPL v2.0, or the
 * CERN-OHL-W v2.
 */

module simtop
#(
	parameter ENABLE_MOSI = 1,
	parameter ENABLE_MISO = 1,
	parameter POLARITY = 0,
	parameter PHASE = 0,
	parameter WID = 24,
	parameter WID_LEN = 5
) (
	input clk,
	input rst_L,

	input [WID-1:0] master_to_slave,
	output [WID-1:0] from_master,

	input [WID-1:0] slave_to_master,
	output [WID-1:0] from_slave,

	input activate,
`ifndef SPI_MASTER_SS
	input ss,
`endif
	input rdy,
	output master_finished,
	output ready_to_arm,
	output err
);

wire miso;

wire mosi;

wire sck;
wire ss_L;

`ifndef SPI_MASTER_SS
assign ss_L = !ss;
`endif

wire slave_finished;
wire slave_error;

`SPI_MASTER_TYPE
#(
`ifdef SPI_MASTER_SS
	.SS_WAIT(5),
	.SS_WAIT_TIMER_LEN(3),
`endif
	.ENABLE_MOSI(ENABLE_MOSI),
	.ENABLE_MISO(ENABLE_MISO),
	.CYCLE_HALF_WAIT(5),
	.TIMER_LEN(3),
	.POLARITY(POLARITY),
	.PHASE(PHASE),
	.WID(WID),
	.WID_LEN(WID_LEN)
) master (
	.clk(clk),
	.rst_L(rst_L),
	.to_slave(master_to_slave),
	.mosi(mosi),
	.from_slave(from_slave),
	.miso(miso),
`ifdef SPI_MASTER_SS
	.ss_L(ss_L),
`endif
	.sck_wire(sck),
	.finished(master_finished),
	.ready_to_arm(ready_to_arm),
	.arm(activate)
);

spi_slave #(
	.ENABLE_MOSI(ENABLE_MOSI),
	.ENABLE_MISO(ENABLE_MISO),
	.POLARITY(POLARITY),
	.PHASE(PHASE),
	.WID(WID),
	.WID_LEN(WID_LEN)
) slave (
	.clk(clk),
	.rst_L(rst_L),
	.sck(sck),
	.ss_L(ss_L),
	.from_master(from_master),
	.mosi(mosi),
	.to_master(slave_to_master),
	.miso(miso),
	.finished(slave_finished),
	.rdy(rdy),
	.err(err)
);

`ifdef SIMULATION
initial begin
	$dumpfile(`VCDFILE);
	$dumpvars;
end
`endif

endmodule