/* (c) Peter McGoron 2022
 * This Source Code Form is subject to the terms of the Mozilla Public
 * License, v.2.0. If a copy of the MPL was not distributed with this
 * file, You can obtain one at https://mozilla.org/MPL/2.0/.
 */

module read_only_mode@MODE@ (
	input clk,
	input activate,
	input ss,
	input rdy,
	output master_finished
);

wire miso;
wire sck;
wire ss_L = !ss;
reg [23:0] from_slave_data;
reg finished;
reg err;

spi_master_no_write
#(
	.POLARITY(@POLARITY@),
	.PHASE(@PHASE@)
) master (
	.clk(clk),
	.from_slave(from_slave_data),
	.miso(miso),
	.sck_wire(sck),
	.finished(master_finished),
	.arm(activate)
);

reg [23:0] to_master = 24'hF4325F;

spi_slave_no_read
#(
	.POLARITY(@POLARITY@),
	.PHASE(@PHASE@)
) slave (
	.clk(clk),
	.sck(sck),
	.ss_L(ss_L),
	.to_master(to_master),
	.miso(miso),
	.finished(finished),
	.rdy(rdy),
	.err(finished)
);

initial begin
	$dumpfile("read_only_mode@MODE@.vcd");
	$dumpvars();
end

endmodule