# Verilog SPI

Verilog SPI master and slave that supports all modes and variable width
via parameters.

## License

This Program is subject to the terms of the Mozilla Public License,
v.2.0. A copy of this license may be found in the file `COPYING`. You
can obtain one at https://mozilla.org/MPL/2.0/.

## Tests

Go into `tests` and run `make`. To rerun tests, run `make clean` followed
by `make`.

The test for each mode generates a `.vcd` file which you may view using
[GTKWave][1]. You can use this to gauge which SPI mode is appropriate for
your device.

[1]: https://gtkwave.sourceforge.net/

## SPI Modes

Modes are denoted by `modePH`, where `P` is the polarity (0 for normal,
1 for inverted) and `H` for phase:

* `H = 0` means the device reads on a rising edge and writes on a falling
  edge.
* `H = 1` means the device reads on a falling edge and writes on a rising
  edge.

Although these modules support all SPI modes, they are labeled slightly
differently from other SPI modes. The phase factor is denoted in terms
of falling and rising edges, not in terms of leading and trailing edges.
This means that polarity also flips the phase term, so a mode 3 device
is a mode 10 device. Devices with regular clock polarity are unaffected,
so a mode 0 device is a mode 00 device, and a mode 1 device is a mode
01 device.