35 lines
618 B
Verilog
35 lines
618 B
Verilog
/* (c) Peter McGoron 2022
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* This Source Code Form is subject to the terms of the Mozilla Public
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* License, v.2.0. If a copy of the MPL was not distributed with this
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* file, You can obtain one at https://mozilla.org/MPL/2.0/.
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*/
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module mode@MODE@ (
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input clk,
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input [23:0] data_ctrl,
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input activate,
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input ss,
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input rdy,
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output master_finished
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);
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spi_write_read
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#(
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.POLARITY(@POLARITY@),
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.PHASE(@PHASE@)
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) base (
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.clk(clk),
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.data_ctrl(data_ctrl),
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.activate(activate),
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.master_finished(master_finished),
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.ss(ss),
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.rdy(rdy)
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);
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initial begin
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$dumpfile("mode@MODE@.vcd");
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$dumpvars();
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end
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endmodule
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