71 lines
1.2 KiB
Verilog
71 lines
1.2 KiB
Verilog
/* (c) Peter McGoron 2022
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* This Source Code Form is subject to the terms of the Mozilla Public
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* License, v.2.0. If a copy of the MPL was not distributed with this
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* file, You can obtain one at https://mozilla.org/MPL/2.0/.
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*/
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module spi_write_read
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#(
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parameter POLARITY = 0,
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parameter PHASE = 0
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)
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(
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input clk,
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input [23:0] data_ctrl,
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input activate,
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input ss,
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input rdy,
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output master_finished
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);
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wire miso;
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wire mosi;
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wire sck;
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wire ss_L = !ss;
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reg [23:0] from_slave_data;
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reg slave_finished;
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reg slave_error;
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spi_master
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#(
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.POLARITY(POLARITY),
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.PHASE(PHASE)
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) master (
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.clk(clk),
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.to_slave(data_ctrl),
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.from_slave(from_slave_data),
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.miso(miso),
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.mosi(mosi),
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.sck_wire(sck),
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.finished(master_finished),
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.arm(activate)
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);
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reg [23:0] data_from_master;
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reg [23:0] data_to_master = 24'b111011011100010101010101;
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spi_slave #(
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.POLARITY(POLARITY),
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.PHASE(PHASE)
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) slave (
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.clk(clk),
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.sck(sck),
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.ss_L(ss_L),
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.from_master(data_from_master),
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.to_master(data_to_master),
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.mosi(mosi),
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.miso(miso),
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.finished(slave_finished),
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.rdy(rdy),
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.err(slave_error)
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);
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always @ (posedge clk) begin
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if (slave_finished) begin
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data_to_master <= data_from_master;
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end
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end
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endmodule
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