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Verilog SPI
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Peter McGoron 6f000b64ec start spi master and slave with testbench 2022-07-20 19:41:54 -04:00
Makefile start spi master and slave with testbench 2022-07-20 19:41:54 -04:00
spi_master.v start spi master and slave with testbench 2022-07-20 19:41:54 -04:00
spi_slave.v start spi master and slave with testbench 2022-07-20 19:41:54 -04:00
test_spi_write_read_mode0.cpp start spi master and slave with testbench 2022-07-20 19:41:54 -04:00
test_spi_write_read_mode0.v start spi master and slave with testbench 2022-07-20 19:41:54 -04:00