138 lines
2.5 KiB
Verilog
138 lines
2.5 KiB
Verilog
/* (c) Peter McGoron 2022 v0.1
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* This Source Code Form is subject to the terms of the Mozilla Public
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* License, v.2.0. If a copy of the MPL was not distributed with this
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* file, You can obtain one at https://mozilla.org/MPL/2.0/.
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*/
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module
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`ifdef SPI_SLAVE_NO_READ
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spi_slave_no_read
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`elsif SPI_SLAVE_NO_WRITE
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spi_slave_no_write
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`else
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spi_slave
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`endif
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#(
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parameter WID = 24, // Width of bits per transaction.
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parameter WID_LEN = 5, // Length in bits required to store WID
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parameter POLARITY = 0,
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parameter PHASE = 0 // 0 = rising-read falling-write, 1 = rising-write falling-read.
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)
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(
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input clk,
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input sck,
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input ss_L,
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`ifndef SPI_SLAVE_NO_READ
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output reg [WID-1:0] from_master,
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input reg mosi,
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`endif
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`ifndef SPI_SLAVE_NO_WRITE
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input [WID-1:0] to_master,
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output reg miso,
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`endif
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output reg finished,
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input rdy,
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output reg err
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);
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wire ss = !ss_L;
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reg sck_delay = 0;
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reg [WID_LEN-1:0] bit_counter = 0;
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reg ss_delay = 0;
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reg ready_at_start = 0;
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`ifndef SPI_SLAVE_NO_WRITE
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reg [WID-1:0] send_buf = 0;
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`endif
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task read_data();
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`ifndef SPI_SLAVE_NO_READ
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from_master <= from_master << 1;
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from_master[0] <= mosi;
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`endif
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endtask
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task write_data();
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`ifndef SPI_SLAVE_NO_WRITE
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send_buf <= send_buf << 1;
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miso <= send_buf[WID-1];
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`endif
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endtask
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task setup_bits();
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`ifndef SPI_SLAVE_NO_WRITE
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/* at Mode 00, the transmission starts with
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* a rising edge, and at mode 11, it starts with a falling
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* edge. For both modes, these are READs.
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*
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* For mode 01 and mode 10, the first action is a WRITE.
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*/
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if (POLARITY == PHASE) begin
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miso <= to_master[WID-1];
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send_buf <= to_master << 1;
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end else begin
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send_buf <= to_master;
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end
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`endif
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endtask
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task check_counter();
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if (bit_counter == WID) begin
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err <= ready_at_start;
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end else begin
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bit_counter <= bit_counter + 1;
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end
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endtask
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always @ (posedge clk) begin
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sck_delay <= sck;
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ss_delay <= ss;
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case ({ss_delay, ss})
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2'b01: begin // rising edge of SS
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bit_counter <= 0;
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finished <= 0;
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err <= 0;
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ready_at_start <= rdy;
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setup_bits();
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end
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2'b10: begin // falling edge
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finished <= ready_at_start;
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end
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2'b11: begin
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case ({sck_delay, sck})
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2'b01: begin // rising edge
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if (PHASE == 1) begin
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write_data();
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end else begin
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read_data();
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end
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if (POLARITY == 0) begin
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check_counter();
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end
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end
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2'b10: begin // falling edge
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if (PHASE == 1) begin
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read_data();
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end else begin
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write_data();
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end
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if (POLARITY == 1) begin
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check_counter();
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end
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end
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default: ;
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endcase
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end
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2'b00: if (!rdy) begin
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finished <= 0;
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err <= 0;
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end
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endcase
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end
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endmodule
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