diff options
| author |  Peter McGoron
| 2022-07-21 01:09:45 -0400 |
|---|---|---|
| committer | Peter McGoron
| 2022-07-21 01:09:45 -0400 |
| commit | c4f401cff2858ec5b0ad3e8d46481f181476ebb2 (patch) | |
| tree | 8f1490fc540527e420acfeb8e1784fbfced99652 | |
| parent | start spi master and slave with testbench (diff) | |
mode 00, write from master to slave works
| -rw-r--r-- | Makefile | 2 | ||||
| -rw-r--r-- | spi_master.v | 26 | ||||
| -rw-r--r-- | spi_slave.v | 22 |
3 files changed, 35 insertions, 15 deletions
@@ -9,7 +9,7 @@ all: obj_dir/V${TESTBENCH_BASE} ./obj_dir/V${TESTBENCH_BASE} && gtkwave ${WAVEFILE} obj_dir/V${TESTBENCH_BASE}.mk: ${FILES} - verilator --trace --cc --exe ${FILES} --top ${TESTBENCH_BASE} + verilator -Wall -Wno-unused -Wpedantic --trace --cc --exe ${FILES} --top ${TESTBENCH_BASE} obj_dir/V${TESTBENCH_BASE}: obj_dir/V${TESTBENCH_BASE}.mk make -C obj_dir -f V${TESTBENCH_BASE}.mk diff --git a/spi_master.v b/spi_master.v index 7bb8db1..baf2f5e 100644 --- a/spi_master.v +++ b/spi_master.v @@ -72,8 +72,22 @@ always @ (posedge clk) begin idle_state(); finished <= 0; end else begin - state <= ON_CYCLE; - send_buf <= to_slave; + /* at Mode 00, the transmission starts with + * a rising edge, and at mode 11, it starts + * with a falling edge. For both modes, + * these are READs. + * + * For mode 01 and mode 10, the first + * action is a WRITE. + */ + if (POLARITY == PHASE) begin + mosi <= to_slave[WID-1]; + send_buf <= to_slave << 1; + state <= CYCLE_WAIT; + end else begin + send_buf <= to_slave; + state <= ON_CYCLE; + end end end ON_CYCLE: begin @@ -84,7 +98,7 @@ always @ (posedge clk) begin read_data(); end - if (POLARITY == 1) begin + if (POLARITY == 0) begin bit_counter <= bit_counter + 1; end end else begin // falling edge @@ -94,7 +108,7 @@ always @ (posedge clk) begin write_data(); end - if (POLARITY == 0) begin + if (POLARITY == 1) begin bit_counter <= bit_counter + 1; end end @@ -103,7 +117,9 @@ always @ (posedge clk) begin CYCLE_WAIT: begin if (timer == CYCLE_HALF_WAIT) begin timer <= 0; - if (bit_counter == WID) begin + // Stop transfer when the clock returns + // to its original polarity. + if (bit_counter == WID && sck == POLARITY) begin state <= WAIT_FINISHED; end else begin state <= ON_CYCLE; diff --git a/spi_slave.v b/spi_slave.v index 7fef528..ec397fb 100644 --- a/spi_slave.v +++ b/spi_slave.v @@ -55,11 +55,7 @@ always @ (posedge clk) begin err <= 0; end 2'b10: begin // falling edge - if (bit_counter == WID) begin - finished <= 1; - end else begin - err <= 1; - end + finished <= 1; end 2'b11: begin case ({sck_delay, sck}) @@ -70,8 +66,12 @@ always @ (posedge clk) begin read_data(); end - if (POLARITY == 1) begin - bit_counter <= bit_counter + 1; + if (POLARITY == 0) begin + if (bit_counter == WID) begin + err <= 1; + end else begin + bit_counter <= bit_counter + 1; + end end end 2'b10: begin // falling edge @@ -81,8 +81,12 @@ always @ (posedge clk) begin write_data(); end - if (POLARITY == 0) begin - bit_counter <= bit_counter + 1; + if (POLARITY == 1) begin + if (bit_counter == WID) begin + err <= 1; + end else begin + bit_counter <= bit_counter + 1; + end end end default: ; |