add ready_to_arm to indiciate when the module can accept another command

1 files changed, 21 insertions, 0 deletions

diff --git a/spi_master.v b/spi_master.v
index 0f07d8a..a69e15b 100644
--- a/spi_master.v
+++ b/spi_master.v
@@ -40,6 +40,7 @@ spi_master
 `endif
 	output reg sck_wire,
 	output reg finished,
+	output reg ready_to_arm,
 	input arm
 );
 
@@ -134,17 +135,28 @@ task cycle_change();
 	end
 endtask
 
+initial ready_to_arm = 1;
+
 always @ (posedge clk) begin
 	case (state)
 	WAIT_ON_ARM: begin
+`ifdef SIMULATION
+		if (!ready_to_arm)
+			$error("not ready to arm in wait_on_arm");
+`endif
 		if (!arm) begin
 			idle_state();
 			finished <= 0;
 		end else begin
 			setup_bits();
+			ready_to_arm <= 0;
 		end
 	end
 	ON_CYCLE: begin
+`ifdef SIMULATION
+		if (ready_to_arm)
+			$error("ready_to_arm while on cycle");
+`endif
 		if (sck) begin // rising edge
 			if (PHASE == 1) begin
 				write_data();
@@ -174,6 +186,10 @@ always @ (posedge clk) begin
 		end
 	end
 	CYCLE_WAIT: begin
+`ifdef SIMULATION
+		if (ready_to_arm)
+			$error("ready_to_arm while in cycle wait");
+`endif
 		if (timer == CYCLE_HALF_WAIT) begin
 			timer <= 1;
 			cycle_change();
@@ -182,10 +198,15 @@ always @ (posedge clk) begin
 		end
 	end
 	WAIT_FINISHED: begin
+`ifdef SIMULATION
+		if (ready_to_arm)
+			$error("ready_to_arm while in wait finished");
+`endif
 		finished <= 1;
 		idle_state();
 		if (!arm) begin
 			state <= WAIT_ON_ARM;
+			ready_to_arm <= 1;
 		end
 	end
 	endcase